# The IMX31PDK eval board has a single IMX31 chip
source [find target/imx31.cfg]
source [find target/imx.cfg]
$_TARGETNAME configure -event reset-init { imx31pdk_init }

proc self_test {} {
	echo "Running 100 iterations of test."
	dump_image /ram/test 0x80000000 0x40000
	for {set i 0} {$i < 100} {set i [expr {$i+1}]} {
		echo "Iteration $i"
		reset init
		mww 0x80000000 0x12345678 0x10000
		load_image /ram/test 0x80000000 bin
		verify_image /ram/test 0x80000000 bin
	}
}


# Slow fallback frequency
# measure_clk indicates ca. 3-4MHz.
jtag_rclk 1000

proc imx31pdk_init { } {

	imx3x_reset

	# This setup puts RAM at 0x80000000

	mww 0x53FC0000 0x040
	mww 0x53F80000 0x074B0B7D

	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
	#mww 0x53F80004 0xFF871D50
	#mww 0x53F80010 0x00271C1B

	# Start 16 bit NorFlash Initialization on CS0
	mww 0xb8002000 0x0000CC03
	mww 0xb8002004 0xa0330D01
	mww 0xb8002008 0x00220800

	# Configure CPLD on CS4
	mww 0xb8002040 0x0000DCF6
	mww 0xb8002044 0x444A4541
	mww 0xb8002048 0x44443302

	# SDCLK
	mww 0x43FAC26C 0

	# CAS
	mww 0x43FAC270 0

	# RAS
	mww 0x43FAC274 0

	# CS2 (CSD0)
	mww 0x43FAC27C 0x1000

	# DQM3
	mww 0x43FAC284 0

	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
	mww 0x43FAC288 0
	mww 0x43FAC28C 0
	mww 0x43FAC290 0
	mww 0x43FAC294 0
	mww 0x43FAC298 0
	mww 0x43FAC29C 0
	mww 0x43FAC2A0 0
	mww 0x43FAC2A4 0
	mww 0x43FAC2A8 0
	mww 0x43FAC2AC 0
	mww 0x43FAC2B0 0
	mww 0x43FAC2B4 0
	mww 0x43FAC2B8 0
	mww 0x43FAC2BC 0
	mww 0x43FAC2C0 0
	mww 0x43FAC2C4 0
	mww 0x43FAC2C8 0
	mww 0x43FAC2CC 0
	mww 0x43FAC2D0 0
	mww 0x43FAC2D4 0
	mww 0x43FAC2D8 0
	mww 0x43FAC2DC 0

	# Initialization script for 32 bit DDR on MX31 ADS
	mww 0xB8001010 0x00000004
	mww 0xB8001004 0x006ac73a
	mww 0xB8001000 0x92100000
	mww 0x80000f00 0x12344321
	mww 0xB8001000 0xa2100000
	mww 0x80000000 0x12344321
	mww 0x80000000 0x12344321
	mww 0xB8001000 0xb2100000
	mwb 0x80000033 0xda
	mwb 0x81000000 0xff
	mww 0xB8001000 0x82226080
	mww 0x80000000 0xDEADBEEF
	mww 0xB8001010 0x0000000c
}
