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core.c 26KB

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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> *
  3. * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
  4. * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> *
  5. * *
  6. * Partially based on drivers/mtd/nand_ids.c from Linux. *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "imp.h"
  27. /* configured NAND devices and NAND Flash command handler */
  28. struct nand_device *nand_devices;
  29. void nand_device_add(struct nand_device *c)
  30. {
  31. if (nand_devices) {
  32. struct nand_device *p = nand_devices;
  33. while (p && p->next)
  34. p = p->next;
  35. p->next = c;
  36. } else
  37. nand_devices = c;
  38. }
  39. /* Chip ID list
  40. *
  41. * Manufacturer, ID code, pagesize, chipsize in MegaByte, eraseblock size,
  42. * options, name
  43. *
  44. * Pagesize; 0, 256, 512
  45. * 0 get this information from the extended chip ID
  46. * 256 256 Byte page size
  47. * 512 512 Byte page size
  48. */
  49. static struct nand_info nand_flash_ids[] = {
  50. /* Vendor Specific Entries */
  51. { NAND_MFR_SAMSUNG, 0xD5, 8192, 2048, 0x100000, LP_OPTIONS,
  52. "K9GAG08 2GB NAND 3.3V x8 MLC 2b/cell"},
  53. { NAND_MFR_SAMSUNG, 0xD7, 8192, 4096, 0x100000, LP_OPTIONS,
  54. "K9LBG08 4GB NAND 3.3V x8 MLC 2b/cell"},
  55. /* start "museum" IDs */
  56. { 0x0, 0x6e, 256, 1, 0x1000, 0, "NAND 1MiB 5V 8-bit"},
  57. { 0x0, 0x64, 256, 2, 0x1000, 0, "NAND 2MiB 5V 8-bit"},
  58. { 0x0, 0x6b, 512, 4, 0x2000, 0, "NAND 4MiB 5V 8-bit"},
  59. { 0x0, 0xe8, 256, 1, 0x1000, 0, "NAND 1MiB 3.3V 8-bit"},
  60. { 0x0, 0xec, 256, 1, 0x1000, 0, "NAND 1MiB 3.3V 8-bit"},
  61. { 0x0, 0xea, 256, 2, 0x1000, 0, "NAND 2MiB 3.3V 8-bit"},
  62. { 0x0, 0xd5, 512, 4, 0x2000, 0, "NAND 4MiB 3.3V 8-bit"},
  63. { 0x0, 0xe3, 512, 4, 0x2000, 0, "NAND 4MiB 3.3V 8-bit"},
  64. { 0x0, 0xe5, 512, 4, 0x2000, 0, "NAND 4MiB 3.3V 8-bit"},
  65. { 0x0, 0xd6, 512, 8, 0x2000, 0, "NAND 8MiB 3.3V 8-bit"},
  66. { 0x0, 0x39, 512, 8, 0x2000, 0, "NAND 8MiB 1.8V 8-bit"},
  67. { 0x0, 0xe6, 512, 8, 0x2000, 0, "NAND 8MiB 3.3V 8-bit"},
  68. { 0x0, 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16, "NAND 8MiB 1.8V 16-bit"},
  69. { 0x0, 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16, "NAND 8MiB 3.3V 16-bit"},
  70. /* end "museum" IDs */
  71. { 0x0, 0x33, 512, 16, 0x4000, 0, "NAND 16MiB 1.8V 8-bit"},
  72. { 0x0, 0x73, 512, 16, 0x4000, 0, "NAND 16MiB 3.3V 8-bit"},
  73. { 0x0, 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16, "NAND 16MiB 1.8V 16-bit"},
  74. { 0x0, 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16, "NAND 16MiB 3.3V 16-bit"},
  75. { 0x0, 0x35, 512, 32, 0x4000, 0, "NAND 32MiB 1.8V 8-bit"},
  76. { 0x0, 0x75, 512, 32, 0x4000, 0, "NAND 32MiB 3.3V 8-bit"},
  77. { 0x0, 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16, "NAND 32MiB 1.8V 16-bit"},
  78. { 0x0, 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16, "NAND 32MiB 3.3V 16-bit"},
  79. { 0x0, 0x36, 512, 64, 0x4000, 0, "NAND 64MiB 1.8V 8-bit"},
  80. { 0x0, 0x76, 512, 64, 0x4000, 0, "NAND 64MiB 3.3V 8-bit"},
  81. { 0x0, 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16, "NAND 64MiB 1.8V 16-bit"},
  82. { 0x0, 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16, "NAND 64MiB 3.3V 16-bit"},
  83. { 0x0, 0x78, 512, 128, 0x4000, 0, "NAND 128MiB 1.8V 8-bit"},
  84. { 0x0, 0x39, 512, 128, 0x4000, 0, "NAND 128MiB 1.8V 8-bit"},
  85. { 0x0, 0x79, 512, 128, 0x4000, 0, "NAND 128MiB 3.3V 8-bit"},
  86. { 0x0, 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 1.8V 16-bit"},
  87. { 0x0, 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 1.8V 16-bit"},
  88. { 0x0, 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 3.3V 16-bit"},
  89. { 0x0, 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 3.3V 16-bit"},
  90. { 0x0, 0x71, 512, 256, 0x4000, 0, "NAND 256MiB 3.3V 8-bit"},
  91. { 0x0, 0xA2, 0, 64, 0, LP_OPTIONS, "NAND 64MiB 1.8V 8-bit"},
  92. { 0x0, 0xF2, 0, 64, 0, LP_OPTIONS, "NAND 64MiB 3.3V 8-bit"},
  93. { 0x0, 0xB2, 0, 64, 0, LP_OPTIONS16, "NAND 64MiB 1.8V 16-bit"},
  94. { 0x0, 0xC2, 0, 64, 0, LP_OPTIONS16, "NAND 64MiB 3.3V 16-bit"},
  95. { 0x0, 0xA1, 0, 128, 0, LP_OPTIONS, "NAND 128MiB 1.8V 8-bit"},
  96. { 0x0, 0xF1, 0, 128, 0, LP_OPTIONS, "NAND 128MiB 3.3V 8-bit"},
  97. { 0x0, 0xB1, 0, 128, 0, LP_OPTIONS16, "NAND 128MiB 1.8V 16-bit"},
  98. { 0x0, 0xC1, 0, 128, 0, LP_OPTIONS16, "NAND 128MiB 3.3V 16-bit"},
  99. { 0x0, 0xAA, 0, 256, 0, LP_OPTIONS, "NAND 256MiB 1.8V 8-bit"},
  100. { 0x0, 0xDA, 0, 256, 0, LP_OPTIONS, "NAND 256MiB 3.3V 8-bit"},
  101. { 0x0, 0xBA, 0, 256, 0, LP_OPTIONS16, "NAND 256MiB 1.8V 16-bit"},
  102. { 0x0, 0xCA, 0, 256, 0, LP_OPTIONS16, "NAND 256MiB 3.3V 16-bit"},
  103. { 0x0, 0xAC, 0, 512, 0, LP_OPTIONS, "NAND 512MiB 1.8V 8-bit"},
  104. { 0x0, 0xDC, 0, 512, 0, LP_OPTIONS, "NAND 512MiB 3.3V 8-bit"},
  105. { 0x0, 0xBC, 0, 512, 0, LP_OPTIONS16, "NAND 512MiB 1.8V 16-bit"},
  106. { 0x0, 0xCC, 0, 512, 0, LP_OPTIONS16, "NAND 512MiB 3.3V 16-bit"},
  107. { 0x0, 0xA3, 0, 1024, 0, LP_OPTIONS, "NAND 1GiB 1.8V 8-bit"},
  108. { 0x0, 0xD3, 0, 1024, 0, LP_OPTIONS, "NAND 1GiB 3.3V 8-bit"},
  109. { 0x0, 0xB3, 0, 1024, 0, LP_OPTIONS16, "NAND 1GiB 1.8V 16-bit"},
  110. { 0x0, 0xC3, 0, 1024, 0, LP_OPTIONS16, "NAND 1GiB 3.3V 16-bit"},
  111. { 0x0, 0xA5, 0, 2048, 0, LP_OPTIONS, "NAND 2GiB 1.8V 8-bit"},
  112. { 0x0, 0xD5, 0, 8192, 0, LP_OPTIONS, "NAND 2GiB 3.3V 8-bit"},
  113. { 0x0, 0xB5, 0, 2048, 0, LP_OPTIONS16, "NAND 2GiB 1.8V 16-bit"},
  114. { 0x0, 0xC5, 0, 2048, 0, LP_OPTIONS16, "NAND 2GiB 3.3V 16-bit"},
  115. { 0x0, 0x48, 0, 2048, 0, LP_OPTIONS, "NAND 2GiB 3.3V 8-bit"},
  116. {0, 0, 0, 0, 0, 0, NULL}
  117. };
  118. /* Manufacturer ID list
  119. */
  120. static struct nand_manufacturer nand_manuf_ids[] = {
  121. {0x0, "unknown"},
  122. {NAND_MFR_TOSHIBA, "Toshiba"},
  123. {NAND_MFR_SAMSUNG, "Samsung"},
  124. {NAND_MFR_FUJITSU, "Fujitsu"},
  125. {NAND_MFR_NATIONAL, "National"},
  126. {NAND_MFR_RENESAS, "Renesas"},
  127. {NAND_MFR_STMICRO, "ST Micro"},
  128. {NAND_MFR_HYNIX, "Hynix"},
  129. {NAND_MFR_MICRON, "Micron"},
  130. {0x0, NULL},
  131. };
  132. /*
  133. * Define default oob placement schemes for large and small page devices
  134. */
  135. #if 0
  136. static struct nand_ecclayout nand_oob_8 = {
  137. .eccbytes = 3,
  138. .eccpos = {0, 1, 2},
  139. .oobfree = {
  140. {.offset = 3,
  141. .length = 2},
  142. {.offset = 6,
  143. .length = 2}
  144. }
  145. };
  146. #endif
  147. /**
  148. * Returns the flash bank specified by @a name, which matches the
  149. * driver name and a suffix (option) specify the driver-specific
  150. * bank number. The suffix consists of the '.' and the driver-specific
  151. * bank number: when two davinci banks are defined, then 'davinci.1' refers
  152. * to the second (e.g. DM355EVM).
  153. */
  154. static struct nand_device *get_nand_device_by_name(const char *name)
  155. {
  156. unsigned requested = get_flash_name_index(name);
  157. unsigned found = 0;
  158. struct nand_device *nand;
  159. for (nand = nand_devices; NULL != nand; nand = nand->next) {
  160. if (strcmp(nand->name, name) == 0)
  161. return nand;
  162. if (!flash_driver_name_matches(nand->controller->name, name))
  163. continue;
  164. if (++found < requested)
  165. continue;
  166. return nand;
  167. }
  168. return NULL;
  169. }
  170. struct nand_device *get_nand_device_by_num(int num)
  171. {
  172. struct nand_device *p;
  173. int i = 0;
  174. for (p = nand_devices; p; p = p->next) {
  175. if (i++ == num)
  176. return p;
  177. }
  178. return NULL;
  179. }
  180. COMMAND_HELPER(nand_command_get_device, unsigned name_index,
  181. struct nand_device **nand)
  182. {
  183. const char *str = CMD_ARGV[name_index];
  184. *nand = get_nand_device_by_name(str);
  185. if (*nand)
  186. return ERROR_OK;
  187. unsigned num;
  188. COMMAND_PARSE_NUMBER(uint, str, num);
  189. *nand = get_nand_device_by_num(num);
  190. if (!*nand) {
  191. command_print(CMD_CTX, "NAND flash device '%s' not found", str);
  192. return ERROR_COMMAND_SYNTAX_ERROR;
  193. }
  194. return ERROR_OK;
  195. }
  196. int nand_build_bbt(struct nand_device *nand, int first, int last)
  197. {
  198. uint32_t page;
  199. int i;
  200. int pages_per_block = (nand->erase_size / nand->page_size);
  201. uint8_t oob[6];
  202. int ret;
  203. if ((first < 0) || (first >= nand->num_blocks))
  204. first = 0;
  205. if ((last >= nand->num_blocks) || (last == -1))
  206. last = nand->num_blocks - 1;
  207. page = first * pages_per_block;
  208. for (i = first; i <= last; i++) {
  209. ret = nand_read_page(nand, page, NULL, 0, oob, 6);
  210. if (ret != ERROR_OK)
  211. return ret;
  212. if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
  213. || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
  214. ((nand->page_size == 2048) && (oob[0] != 0xff)))) {
  215. LOG_WARNING("bad block: %i", i);
  216. nand->blocks[i].is_bad = 1;
  217. } else
  218. nand->blocks[i].is_bad = 0;
  219. page += pages_per_block;
  220. }
  221. return ERROR_OK;
  222. }
  223. int nand_read_status(struct nand_device *nand, uint8_t *status)
  224. {
  225. if (!nand->device)
  226. return ERROR_NAND_DEVICE_NOT_PROBED;
  227. /* Send read status command */
  228. nand->controller->command(nand, NAND_CMD_STATUS);
  229. alive_sleep(1);
  230. /* read status */
  231. if (nand->device->options & NAND_BUSWIDTH_16) {
  232. uint16_t data;
  233. nand->controller->read_data(nand, &data);
  234. *status = data & 0xff;
  235. } else
  236. nand->controller->read_data(nand, status);
  237. return ERROR_OK;
  238. }
  239. static int nand_poll_ready(struct nand_device *nand, int timeout)
  240. {
  241. uint8_t status;
  242. nand->controller->command(nand, NAND_CMD_STATUS);
  243. do {
  244. if (nand->device->options & NAND_BUSWIDTH_16) {
  245. uint16_t data;
  246. nand->controller->read_data(nand, &data);
  247. status = data & 0xff;
  248. } else
  249. nand->controller->read_data(nand, &status);
  250. if (status & NAND_STATUS_READY)
  251. break;
  252. alive_sleep(1);
  253. } while (timeout--);
  254. return (status & NAND_STATUS_READY) != 0;
  255. }
  256. int nand_probe(struct nand_device *nand)
  257. {
  258. uint8_t manufacturer_id, device_id;
  259. uint8_t id_buff[6];
  260. int retval;
  261. int i;
  262. /* clear device data */
  263. nand->device = NULL;
  264. nand->manufacturer = NULL;
  265. /* clear device parameters */
  266. nand->bus_width = 0;
  267. nand->address_cycles = 0;
  268. nand->page_size = 0;
  269. nand->erase_size = 0;
  270. /* initialize controller (device parameters are zero, use controller default) */
  271. retval = nand->controller->init(nand);
  272. if (retval != ERROR_OK) {
  273. switch (retval) {
  274. case ERROR_NAND_OPERATION_FAILED:
  275. LOG_DEBUG("controller initialization failed");
  276. return ERROR_NAND_OPERATION_FAILED;
  277. case ERROR_NAND_OPERATION_NOT_SUPPORTED:
  278. LOG_ERROR(
  279. "BUG: controller reported that it doesn't support default parameters");
  280. return ERROR_NAND_OPERATION_FAILED;
  281. default:
  282. LOG_ERROR("BUG: unknown controller initialization failure");
  283. return ERROR_NAND_OPERATION_FAILED;
  284. }
  285. }
  286. nand->controller->command(nand, NAND_CMD_RESET);
  287. nand->controller->reset(nand);
  288. nand->controller->command(nand, NAND_CMD_READID);
  289. nand->controller->address(nand, 0x0);
  290. if (nand->bus_width == 8) {
  291. nand->controller->read_data(nand, &manufacturer_id);
  292. nand->controller->read_data(nand, &device_id);
  293. } else {
  294. uint16_t data_buf;
  295. nand->controller->read_data(nand, &data_buf);
  296. manufacturer_id = data_buf & 0xff;
  297. nand->controller->read_data(nand, &data_buf);
  298. device_id = data_buf & 0xff;
  299. }
  300. for (i = 0; nand_flash_ids[i].name; i++) {
  301. if (nand_flash_ids[i].id == device_id &&
  302. (nand_flash_ids[i].mfr_id == manufacturer_id ||
  303. nand_flash_ids[i].mfr_id == 0)) {
  304. nand->device = &nand_flash_ids[i];
  305. break;
  306. }
  307. }
  308. for (i = 0; nand_manuf_ids[i].name; i++) {
  309. if (nand_manuf_ids[i].id == manufacturer_id) {
  310. nand->manufacturer = &nand_manuf_ids[i];
  311. break;
  312. }
  313. }
  314. if (!nand->manufacturer) {
  315. nand->manufacturer = &nand_manuf_ids[0];
  316. nand->manufacturer->id = manufacturer_id;
  317. }
  318. if (!nand->device) {
  319. LOG_ERROR(
  320. "unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
  321. manufacturer_id,
  322. device_id);
  323. return ERROR_NAND_OPERATION_FAILED;
  324. }
  325. LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
  326. /* initialize device parameters */
  327. /* bus width */
  328. if (nand->device->options & NAND_BUSWIDTH_16)
  329. nand->bus_width = 16;
  330. else
  331. nand->bus_width = 8;
  332. /* Do we need extended device probe information? */
  333. if (nand->device->page_size == 0 ||
  334. nand->device->erase_size == 0) {
  335. if (nand->bus_width == 8) {
  336. nand->controller->read_data(nand, id_buff + 3);
  337. nand->controller->read_data(nand, id_buff + 4);
  338. nand->controller->read_data(nand, id_buff + 5);
  339. } else {
  340. uint16_t data_buf;
  341. nand->controller->read_data(nand, &data_buf);
  342. id_buff[3] = data_buf;
  343. nand->controller->read_data(nand, &data_buf);
  344. id_buff[4] = data_buf;
  345. nand->controller->read_data(nand, &data_buf);
  346. id_buff[5] = data_buf >> 8;
  347. }
  348. }
  349. /* page size */
  350. if (nand->device->page_size == 0)
  351. nand->page_size = 1 << (10 + (id_buff[4] & 3));
  352. else if (nand->device->page_size == 256) {
  353. LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
  354. return ERROR_NAND_OPERATION_FAILED;
  355. } else
  356. nand->page_size = nand->device->page_size;
  357. /* number of address cycles */
  358. if (nand->page_size <= 512) {
  359. /* small page devices */
  360. if (nand->device->chip_size <= 32)
  361. nand->address_cycles = 3;
  362. else if (nand->device->chip_size <= 8*1024)
  363. nand->address_cycles = 4;
  364. else {
  365. LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
  366. nand->address_cycles = 5;
  367. }
  368. } else {
  369. /* large page devices */
  370. if (nand->device->chip_size <= 128)
  371. nand->address_cycles = 4;
  372. else if (nand->device->chip_size <= 32*1024)
  373. nand->address_cycles = 5;
  374. else {
  375. LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
  376. nand->address_cycles = 6;
  377. }
  378. }
  379. /* erase size */
  380. if (nand->device->erase_size == 0) {
  381. switch ((id_buff[4] >> 4) & 3) {
  382. case 0:
  383. nand->erase_size = 64 << 10;
  384. break;
  385. case 1:
  386. nand->erase_size = 128 << 10;
  387. break;
  388. case 2:
  389. nand->erase_size = 256 << 10;
  390. break;
  391. case 3:
  392. nand->erase_size = 512 << 10;
  393. break;
  394. }
  395. } else
  396. nand->erase_size = nand->device->erase_size;
  397. /* initialize controller, but leave parameters at the controllers default */
  398. retval = nand->controller->init(nand);
  399. if (retval != ERROR_OK) {
  400. switch (retval) {
  401. case ERROR_NAND_OPERATION_FAILED:
  402. LOG_DEBUG("controller initialization failed");
  403. return ERROR_NAND_OPERATION_FAILED;
  404. case ERROR_NAND_OPERATION_NOT_SUPPORTED:
  405. LOG_ERROR(
  406. "controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
  407. nand->bus_width,
  408. nand->address_cycles,
  409. nand->page_size);
  410. return ERROR_NAND_OPERATION_FAILED;
  411. default:
  412. LOG_ERROR("BUG: unknown controller initialization failure");
  413. return ERROR_NAND_OPERATION_FAILED;
  414. }
  415. }
  416. nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
  417. nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
  418. for (i = 0; i < nand->num_blocks; i++) {
  419. nand->blocks[i].size = nand->erase_size;
  420. nand->blocks[i].offset = i * nand->erase_size;
  421. nand->blocks[i].is_erased = -1;
  422. nand->blocks[i].is_bad = -1;
  423. }
  424. return ERROR_OK;
  425. }
  426. int nand_erase(struct nand_device *nand, int first_block, int last_block)
  427. {
  428. int i;
  429. uint32_t page;
  430. uint8_t status;
  431. int retval;
  432. if (!nand->device)
  433. return ERROR_NAND_DEVICE_NOT_PROBED;
  434. if ((first_block < 0) || (last_block >= nand->num_blocks))
  435. return ERROR_COMMAND_SYNTAX_ERROR;
  436. /* make sure we know if a block is bad before erasing it */
  437. for (i = first_block; i <= last_block; i++) {
  438. if (nand->blocks[i].is_bad == -1) {
  439. nand_build_bbt(nand, i, last_block);
  440. break;
  441. }
  442. }
  443. for (i = first_block; i <= last_block; i++) {
  444. /* Send erase setup command */
  445. nand->controller->command(nand, NAND_CMD_ERASE1);
  446. page = i * (nand->erase_size / nand->page_size);
  447. /* Send page address */
  448. if (nand->page_size <= 512) {
  449. /* row */
  450. nand->controller->address(nand, page & 0xff);
  451. nand->controller->address(nand, (page >> 8) & 0xff);
  452. /* 3rd cycle only on devices with more than 32 MiB */
  453. if (nand->address_cycles >= 4)
  454. nand->controller->address(nand, (page >> 16) & 0xff);
  455. /* 4th cycle only on devices with more than 8 GiB */
  456. if (nand->address_cycles >= 5)
  457. nand->controller->address(nand, (page >> 24) & 0xff);
  458. } else {
  459. /* row */
  460. nand->controller->address(nand, page & 0xff);
  461. nand->controller->address(nand, (page >> 8) & 0xff);
  462. /* 3rd cycle only on devices with more than 128 MiB */
  463. if (nand->address_cycles >= 5)
  464. nand->controller->address(nand, (page >> 16) & 0xff);
  465. }
  466. /* Send erase confirm command */
  467. nand->controller->command(nand, NAND_CMD_ERASE2);
  468. retval = nand->controller->nand_ready ?
  469. nand->controller->nand_ready(nand, 1000) :
  470. nand_poll_ready(nand, 1000);
  471. if (!retval) {
  472. LOG_ERROR("timeout waiting for NAND flash block erase to complete");
  473. return ERROR_NAND_OPERATION_TIMEOUT;
  474. }
  475. retval = nand_read_status(nand, &status);
  476. if (retval != ERROR_OK) {
  477. LOG_ERROR("couldn't read status");
  478. return ERROR_NAND_OPERATION_FAILED;
  479. }
  480. if (status & 0x1) {
  481. LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
  482. (nand->blocks[i].is_bad == 1)
  483. ? "bad " : "",
  484. i, status);
  485. /* continue; other blocks might still be erasable */
  486. }
  487. nand->blocks[i].is_erased = 1;
  488. }
  489. return ERROR_OK;
  490. }
  491. #if 0
  492. static int nand_read_plain(struct nand_device *nand,
  493. uint32_t address,
  494. uint8_t *data,
  495. uint32_t data_size)
  496. {
  497. uint8_t *page;
  498. if (!nand->device)
  499. return ERROR_NAND_DEVICE_NOT_PROBED;
  500. if (address % nand->page_size) {
  501. LOG_ERROR("reads need to be page aligned");
  502. return ERROR_NAND_OPERATION_FAILED;
  503. }
  504. page = malloc(nand->page_size);
  505. while (data_size > 0) {
  506. uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
  507. uint32_t page_address;
  508. page_address = address / nand->page_size;
  509. nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
  510. memcpy(data, page, thisrun_size);
  511. address += thisrun_size;
  512. data += thisrun_size;
  513. data_size -= thisrun_size;
  514. }
  515. free(page);
  516. return ERROR_OK;
  517. }
  518. static int nand_write_plain(struct nand_device *nand,
  519. uint32_t address,
  520. uint8_t *data,
  521. uint32_t data_size)
  522. {
  523. uint8_t *page;
  524. if (!nand->device)
  525. return ERROR_NAND_DEVICE_NOT_PROBED;
  526. if (address % nand->page_size) {
  527. LOG_ERROR("writes need to be page aligned");
  528. return ERROR_NAND_OPERATION_FAILED;
  529. }
  530. page = malloc(nand->page_size);
  531. while (data_size > 0) {
  532. uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
  533. uint32_t page_address;
  534. memset(page, 0xff, nand->page_size);
  535. memcpy(page, data, thisrun_size);
  536. page_address = address / nand->page_size;
  537. nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
  538. address += thisrun_size;
  539. data += thisrun_size;
  540. data_size -= thisrun_size;
  541. }
  542. free(page);
  543. return ERROR_OK;
  544. }
  545. #endif
  546. int nand_write_page(struct nand_device *nand, uint32_t page,
  547. uint8_t *data, uint32_t data_size,
  548. uint8_t *oob, uint32_t oob_size)
  549. {
  550. uint32_t block;
  551. if (!nand->device)
  552. return ERROR_NAND_DEVICE_NOT_PROBED;
  553. block = page / (nand->erase_size / nand->page_size);
  554. if (nand->blocks[block].is_erased == 1)
  555. nand->blocks[block].is_erased = 0;
  556. if (nand->use_raw || nand->controller->write_page == NULL)
  557. return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
  558. else
  559. return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
  560. }
  561. int nand_read_page(struct nand_device *nand, uint32_t page,
  562. uint8_t *data, uint32_t data_size,
  563. uint8_t *oob, uint32_t oob_size)
  564. {
  565. if (!nand->device)
  566. return ERROR_NAND_DEVICE_NOT_PROBED;
  567. if (nand->use_raw || nand->controller->read_page == NULL)
  568. return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
  569. else
  570. return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
  571. }
  572. int nand_page_command(struct nand_device *nand, uint32_t page,
  573. uint8_t cmd, bool oob_only)
  574. {
  575. if (!nand->device)
  576. return ERROR_NAND_DEVICE_NOT_PROBED;
  577. if (oob_only && NAND_CMD_READ0 == cmd && nand->page_size <= 512)
  578. cmd = NAND_CMD_READOOB;
  579. nand->controller->command(nand, cmd);
  580. if (nand->page_size <= 512) {
  581. /* small page device */
  582. /* column (always 0, we start at the beginning of a page/OOB area) */
  583. nand->controller->address(nand, 0x0);
  584. /* row */
  585. nand->controller->address(nand, page & 0xff);
  586. nand->controller->address(nand, (page >> 8) & 0xff);
  587. /* 4th cycle only on devices with more than 32 MiB */
  588. if (nand->address_cycles >= 4)
  589. nand->controller->address(nand, (page >> 16) & 0xff);
  590. /* 5th cycle only on devices with more than 8 GiB */
  591. if (nand->address_cycles >= 5)
  592. nand->controller->address(nand, (page >> 24) & 0xff);
  593. } else {
  594. /* large page device */
  595. /* column (0 when we start at the beginning of a page,
  596. * or 2048 for the beginning of OOB area)
  597. */
  598. nand->controller->address(nand, 0x0);
  599. if (oob_only)
  600. nand->controller->address(nand, 0x8);
  601. else
  602. nand->controller->address(nand, 0x0);
  603. /* row */
  604. nand->controller->address(nand, page & 0xff);
  605. nand->controller->address(nand, (page >> 8) & 0xff);
  606. /* 5th cycle only on devices with more than 128 MiB */
  607. if (nand->address_cycles >= 5)
  608. nand->controller->address(nand, (page >> 16) & 0xff);
  609. /* large page devices need a start command if reading */
  610. if (NAND_CMD_READ0 == cmd)
  611. nand->controller->command(nand, NAND_CMD_READSTART);
  612. }
  613. if (nand->controller->nand_ready) {
  614. if (!nand->controller->nand_ready(nand, 100))
  615. return ERROR_NAND_OPERATION_TIMEOUT;
  616. } else {
  617. /* nand_poll_read() cannot be used during nand read */
  618. alive_sleep(1);
  619. }
  620. return ERROR_OK;
  621. }
  622. int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
  623. {
  624. int retval = ERROR_NAND_NO_BUFFER;
  625. if (nand->controller->read_block_data != NULL)
  626. retval = (nand->controller->read_block_data)(nand, data, size);
  627. if (ERROR_NAND_NO_BUFFER == retval) {
  628. uint32_t i;
  629. int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1;
  630. retval = ERROR_OK;
  631. for (i = 0; retval == ERROR_OK && i < size; i += incr) {
  632. retval = nand->controller->read_data(nand, data);
  633. data += incr;
  634. }
  635. }
  636. return retval;
  637. }
  638. int nand_read_page_raw(struct nand_device *nand, uint32_t page,
  639. uint8_t *data, uint32_t data_size,
  640. uint8_t *oob, uint32_t oob_size)
  641. {
  642. int retval;
  643. retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
  644. if (ERROR_OK != retval)
  645. return retval;
  646. if (data)
  647. nand_read_data_page(nand, data, data_size);
  648. if (oob)
  649. nand_read_data_page(nand, oob, oob_size);
  650. return ERROR_OK;
  651. }
  652. int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
  653. {
  654. int retval = ERROR_NAND_NO_BUFFER;
  655. if (nand->controller->write_block_data != NULL)
  656. retval = (nand->controller->write_block_data)(nand, data, size);
  657. if (ERROR_NAND_NO_BUFFER == retval) {
  658. bool is16bit = nand->device->options & NAND_BUSWIDTH_16;
  659. uint32_t incr = is16bit ? 2 : 1;
  660. uint16_t write_data;
  661. uint32_t i;
  662. for (i = 0; i < size; i += incr) {
  663. if (is16bit)
  664. write_data = le_to_h_u16(data);
  665. else
  666. write_data = *data;
  667. retval = nand->controller->write_data(nand, write_data);
  668. if (ERROR_OK != retval)
  669. break;
  670. data += incr;
  671. }
  672. }
  673. return retval;
  674. }
  675. int nand_write_finish(struct nand_device *nand)
  676. {
  677. int retval;
  678. uint8_t status;
  679. nand->controller->command(nand, NAND_CMD_PAGEPROG);
  680. retval = nand->controller->nand_ready ?
  681. nand->controller->nand_ready(nand, 100) :
  682. nand_poll_ready(nand, 100);
  683. if (!retval)
  684. return ERROR_NAND_OPERATION_TIMEOUT;
  685. retval = nand_read_status(nand, &status);
  686. if (ERROR_OK != retval) {
  687. LOG_ERROR("couldn't read status");
  688. return ERROR_NAND_OPERATION_FAILED;
  689. }
  690. if (status & NAND_STATUS_FAIL) {
  691. LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
  692. status);
  693. return ERROR_NAND_OPERATION_FAILED;
  694. }
  695. return ERROR_OK;
  696. }
  697. int nand_write_page_raw(struct nand_device *nand, uint32_t page,
  698. uint8_t *data, uint32_t data_size,
  699. uint8_t *oob, uint32_t oob_size)
  700. {
  701. int retval;
  702. retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
  703. if (ERROR_OK != retval)
  704. return retval;
  705. if (data) {
  706. retval = nand_write_data_page(nand, data, data_size);
  707. if (ERROR_OK != retval) {
  708. LOG_ERROR("Unable to write data to NAND device");
  709. return retval;
  710. }
  711. }
  712. if (oob) {
  713. retval = nand_write_data_page(nand, oob, oob_size);
  714. if (ERROR_OK != retval) {
  715. LOG_ERROR("Unable to write OOB data to NAND device");
  716. return retval;
  717. }
  718. }
  719. return nand_write_finish(nand);
  720. }