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ti_tms570.cfg 1.9 KiB

target/ti_tms570.cfg: added several JTAG IDs for TMS570LS family from TI datasheets for whole cortex-r4 family added JTAG IDs TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns192 0x0B95502F 16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B) http://www.ti.com/lit/pdf/spns230 0x0D8A002F 0x2D8A002F 0x3D8A002F RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns177 0x0D8A002F 0x2D8A002F 0x3D8A002F RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns185 0x0B95502F RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns176 0x0B8A002F 0x2B8A002F 0x3B8A002F RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns182 0x0B95502F RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns184 0x0B95502F TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns186 0x0B97102F RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns180 0x0B97102F RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/ 0x0B95502F TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns191 0x0B95502F RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns175 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns165 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F) http://www.ti.com/lit/pdf/spns141 0x0B7B302F TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns164 0x0B8A002F 0x2B8A002F 0x3B8A002F RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns174 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns162 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns190 0x0B95502F TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns189 0x0B95502F TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns188 0x0B95502F Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c Signed-off-by: Jiri Kastner <cz172638@gmail.com> Tested-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/2123 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
8 years ago
target/ti_tms570.cfg: added several JTAG IDs for TMS570LS family from TI datasheets for whole cortex-r4 family added JTAG IDs TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns192 0x0B95502F 16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B) http://www.ti.com/lit/pdf/spns230 0x0D8A002F 0x2D8A002F 0x3D8A002F RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns177 0x0D8A002F 0x2D8A002F 0x3D8A002F RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns185 0x0B95502F RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns176 0x0B8A002F 0x2B8A002F 0x3B8A002F RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns182 0x0B95502F RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns184 0x0B95502F TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns186 0x0B97102F RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns180 0x0B97102F RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/ 0x0B95502F TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns191 0x0B95502F RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns175 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns165 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F) http://www.ti.com/lit/pdf/spns141 0x0B7B302F TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns164 0x0B8A002F 0x2B8A002F 0x3B8A002F RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns174 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns162 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns190 0x0B95502F TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns189 0x0B95502F TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns188 0x0B95502F Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c Signed-off-by: Jiri Kastner <cz172638@gmail.com> Tested-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/2123 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
8 years ago
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  1. adapter_khz 1500
  2. if { [info exists CHIPNAME] } {
  3. set _CHIPNAME $CHIPNAME
  4. } else {
  5. set _CHIPNAME tms570
  6. }
  7. if { [info exists ENDIAN] } {
  8. set _ENDIAN $ENDIAN
  9. } else {
  10. set _ENDIAN big
  11. }
  12. # TMS570 has an ICEpick-C on which we need the router commands.
  13. source [find target/icepick.cfg]
  14. # Main DAP
  15. # DAP_TAPID should be set before source-ing this file
  16. if { [info exists DAP_TAPID] } {
  17. set _DAP_TAPID $DAP_TAPID
  18. }
  19. jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
  20. jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
  21. # ICEpick-C (JTAG route controller)
  22. # JRC_TAPID should be set before source-ing this file
  23. if { [info exists JRC_TAPID] } {
  24. set _JRC_TAPID $JRC_TAPID
  25. }
  26. set _JRC_TAPID2 0x0B7B302F
  27. set _JRC_TAPID3 0x0B95502F
  28. set _JRC_TAPID4 0x0B97102F
  29. set _JRC_TAPID5 0x0D8A002F
  30. set _JRC_TAPID6 0x2B8A002F
  31. set _JRC_TAPID7 0x2D8A002F
  32. set _JRC_TAPID8 0x3B8A002F
  33. set _JRC_TAPID9 0x3D8A002F
  34. jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  35. -expected-id $_JRC_TAPID \
  36. -expected-id $_JRC_TAPID2 \
  37. -expected-id $_JRC_TAPID3 \
  38. -expected-id $_JRC_TAPID4 \
  39. -expected-id $_JRC_TAPID5 \
  40. -expected-id $_JRC_TAPID6 \
  41. -expected-id $_JRC_TAPID7 \
  42. -expected-id $_JRC_TAPID8 \
  43. -expected-id $_JRC_TAPID9 \
  44. -ignore-version
  45. jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
  46. jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
  47. # Cortex R4 target
  48. set _TARGETNAME $_CHIPNAME.cpu
  49. target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
  50. -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
  51. # TMS570 uses quirky BE-32 mode
  52. $_TARGETNAME dap ti_be_32_quirks 1
  53. $_TARGETNAME configure -event gdb-attach {
  54. cortex_r4 dbginit
  55. halt
  56. }
  57. $_TARGETNAME configure -event "reset-assert" {
  58. global _CHIPNAME
  59. # assert warm system reset through ICEPick
  60. icepick_c_wreset $_CHIPNAME.jrc
  61. }