You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

mips_ejtag.c 9.8 KiB

mips: m4k alternate pracc code. Patch 1 This patch and the following patches define another way of doing processor access without the need to read back the pracc address as needed in current pracc code. Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200 and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start. Most of the processor accesses are fetch and some are store accesses. After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses. The pracc address for a store depends only on the store instruction given before. m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline. For reference: MD00249 mips32 m4k manual. A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by current code or by the new one to generate the sequence of pracc accesses. For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96(). This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution. The pracc bit is not checked before execution, is checked after the queue has been executed. Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay between scans is added by calling jtag_add_cloks(). A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it. A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set, current code is executed, if lower, new code is executed. Initial default values are set in function mips32_init_arch_info. A reset does not change this settings. Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1193 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
9 years ago
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364
  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "mips32.h"
  28. #include "mips_ejtag.h"
  29. void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
  30. {
  31. struct jtag_tap *tap;
  32. tap = ejtag_info->tap;
  33. assert(tap != NULL);
  34. if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
  35. struct scan_field field;
  36. uint8_t t[4];
  37. field.num_bits = tap->ir_length;
  38. field.out_value = t;
  39. buf_set_u32(t, 0, field.num_bits, new_instr);
  40. field.in_value = NULL;
  41. jtag_add_ir_scan(tap, &field, TAP_IDLE);
  42. }
  43. }
  44. int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
  45. {
  46. struct scan_field field;
  47. uint8_t r[4];
  48. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
  49. field.num_bits = 32;
  50. field.out_value = NULL;
  51. field.in_value = r;
  52. jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  53. int retval;
  54. retval = jtag_execute_queue();
  55. if (retval != ERROR_OK) {
  56. LOG_ERROR("register read failed");
  57. return retval;
  58. }
  59. *idcode = buf_get_u32(field.in_value, 0, 32);
  60. return ERROR_OK;
  61. }
  62. static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
  63. {
  64. struct scan_field field;
  65. uint8_t r[4];
  66. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
  67. field.num_bits = 32;
  68. field.out_value = NULL;
  69. field.in_value = r;
  70. jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  71. int retval;
  72. retval = jtag_execute_queue();
  73. if (retval != ERROR_OK) {
  74. LOG_ERROR("register read failed");
  75. return retval;
  76. }
  77. *impcode = buf_get_u32(field.in_value, 0, 32);
  78. return ERROR_OK;
  79. }
  80. void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
  81. {
  82. assert(ejtag_info->tap != NULL);
  83. struct jtag_tap *tap = ejtag_info->tap;
  84. struct scan_field field;
  85. uint8_t out_scan[12];
  86. /* processor access "all" register 96 bit */
  87. field.num_bits = 96;
  88. field.out_value = out_scan;
  89. buf_set_u32(out_scan, 0, 32, ctrl);
  90. buf_set_u32(out_scan + 4, 0, 32, data);
  91. buf_set_u32(out_scan + 8, 0, 32, 0);
  92. field.in_value = in_scan_buf;
  93. jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
  94. keep_alive();
  95. }
  96. int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
  97. {
  98. struct jtag_tap *tap;
  99. tap = ejtag_info->tap;
  100. assert(tap != NULL);
  101. struct scan_field field;
  102. uint8_t t[4], r[4];
  103. int retval;
  104. field.num_bits = 32;
  105. field.out_value = t;
  106. buf_set_u32(t, 0, field.num_bits, *data);
  107. field.in_value = r;
  108. jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
  109. retval = jtag_execute_queue();
  110. if (retval != ERROR_OK) {
  111. LOG_ERROR("register read failed");
  112. return retval;
  113. }
  114. *data = buf_get_u32(field.in_value, 0, 32);
  115. keep_alive();
  116. return ERROR_OK;
  117. }
  118. void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
  119. {
  120. uint8_t t[4];
  121. struct jtag_tap *tap;
  122. tap = ejtag_info->tap;
  123. assert(tap != NULL);
  124. struct scan_field field;
  125. field.num_bits = 32;
  126. field.out_value = t;
  127. buf_set_u32(t, 0, field.num_bits, data);
  128. field.in_value = NULL;
  129. jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
  130. }
  131. int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
  132. {
  133. struct jtag_tap *tap;
  134. tap = ejtag_info->tap;
  135. assert(tap != NULL);
  136. struct scan_field field;
  137. uint8_t t[4] = {0, 0, 0, 0}, r[4];
  138. int retval;
  139. field.num_bits = 8;
  140. field.out_value = t;
  141. buf_set_u32(t, 0, field.num_bits, *data);
  142. field.in_value = r;
  143. jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
  144. retval = jtag_execute_queue();
  145. if (retval != ERROR_OK) {
  146. LOG_ERROR("register read failed");
  147. return retval;
  148. }
  149. *data = buf_get_u32(field.in_value, 0, 32);
  150. return ERROR_OK;
  151. }
  152. void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
  153. {
  154. struct jtag_tap *tap;
  155. tap = ejtag_info->tap;
  156. assert(tap != NULL);
  157. struct scan_field field;
  158. field.num_bits = 8;
  159. field.out_value = &data;
  160. field.in_value = NULL;
  161. jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
  162. }
  163. /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
  164. int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
  165. {
  166. struct pracc_queue_info ctx = {.max_code = 7};
  167. pracc_queue_init(&ctx);
  168. if (ctx.retval != ERROR_OK)
  169. goto exit;
  170. pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
  171. pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
  172. if (!enable_step)
  173. pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
  174. pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
  175. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
  176. pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
  177. pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
  178. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
  179. exit:
  180. pracc_queue_free(&ctx);
  181. return ctx.retval;
  182. }
  183. int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
  184. {
  185. uint32_t ejtag_ctrl;
  186. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  187. /* set debug break bit */
  188. ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
  189. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  190. /* break bit will be cleared by hardware */
  191. ejtag_ctrl = ejtag_info->ejtag_ctrl;
  192. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  193. LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
  194. if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) {
  195. LOG_ERROR("Failed to enter Debug Mode!");
  196. return ERROR_FAIL;
  197. }
  198. return ERROR_OK;
  199. }
  200. int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
  201. {
  202. uint32_t instr = MIPS32_DRET;
  203. struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &instr, .code_count = 1, .store_count = 0};
  204. /* execute our dret instruction */
  205. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
  206. /* pic32mx workaround, false pending at low core clock */
  207. jtag_add_sleep(1000);
  208. return ctx.retval;
  209. }
  210. int mips_ejtag_init(struct mips_ejtag *ejtag_info)
  211. {
  212. uint32_t ejtag_version;
  213. int retval;
  214. retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
  215. if (retval != ERROR_OK)
  216. return retval;
  217. LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
  218. /* get ejtag version */
  219. ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
  220. switch (ejtag_version) {
  221. case 0:
  222. LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
  223. break;
  224. case 1:
  225. LOG_DEBUG("EJTAG: Version 2.5 Detected");
  226. break;
  227. case 2:
  228. LOG_DEBUG("EJTAG: Version 2.6 Detected");
  229. break;
  230. case 3:
  231. LOG_DEBUG("EJTAG: Version 3.1 Detected");
  232. break;
  233. case 4:
  234. LOG_DEBUG("EJTAG: Version 4.1 Detected");
  235. break;
  236. case 5:
  237. LOG_DEBUG("EJTAG: Version 5.1 Detected");
  238. break;
  239. default:
  240. LOG_DEBUG("EJTAG: Unknown Version Detected");
  241. break;
  242. }
  243. LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
  244. ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
  245. ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
  246. ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
  247. ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
  248. ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
  249. ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
  250. ejtag_info->impcode & EJTAG_DCR_MIPS64 ? " MIPS64" : " MIPS32");
  251. if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
  252. LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
  253. /* set initial state for ejtag control reg */
  254. ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
  255. ejtag_info->fast_access_save = -1;
  256. return ERROR_OK;
  257. }
  258. int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
  259. {
  260. struct jtag_tap *tap;
  261. tap = ejtag_info->tap;
  262. assert(tap != NULL);
  263. struct scan_field fields[2];
  264. uint8_t spracc = 0;
  265. uint8_t t[4] = {0, 0, 0, 0};
  266. /* fastdata 1-bit register */
  267. fields[0].num_bits = 1;
  268. fields[0].out_value = &spracc;
  269. fields[0].in_value = NULL;
  270. /* processor access data register 32 bit */
  271. fields[1].num_bits = 32;
  272. fields[1].out_value = t;
  273. if (write_t) {
  274. fields[1].in_value = NULL;
  275. buf_set_u32(t, 0, 32, *data);
  276. } else
  277. fields[1].in_value = (void *) data;
  278. jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
  279. if (!write_t && data)
  280. jtag_add_callback(mips_le_to_h_u32,
  281. (jtag_callback_data_t) data);
  282. keep_alive();
  283. return ERROR_OK;
  284. }