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at91sam9260_ext_RAM_ext_flash.cfg 3.7 KiB

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  1. jtag_khz 4
  2. ######################################
  3. # Target: Atmel AT91SAM9260
  4. ######################################
  5. if { [info exists CHIPNAME] } {
  6. set _CHIPNAME $CHIPNAME
  7. } else {
  8. set _CHIPNAME at91sam9260
  9. }
  10. if { [info exists ENDIAN] } {
  11. set _ENDIAN $ENDIAN
  12. } else {
  13. set _ENDIAN little
  14. }
  15. if { [info exists CPUTAPID ] } {
  16. set _CPUTAPID $CPUTAPID
  17. } else {
  18. # force an error till we get a good number
  19. set _CPUTAPID 0x0792603f
  20. }
  21. reset_config trst_and_srst
  22. jtag_nsrst_delay 200
  23. jtag_ntrst_delay 200
  24. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  25. ######################
  26. # Target configuration
  27. ######################
  28. set _TARGETNAME $_CHIPNAME.cpu
  29. target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
  30. $_TARGETNAME invoke-event halted
  31. # Internal sram1 memory
  32. $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
  33. scan_chain
  34. $_TARGETNAME configure -event reset-deassert-post {at91sam_init}
  35. # Flash configuration
  36. #flash bank cfi <base> <size> <chip width> <bus width> <target#>
  37. flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
  38. proc at91sam_init { } {
  39. # at reset chip runs at 32khz
  40. jtag_khz 8
  41. halt
  42. mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
  43. mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
  44. mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
  45. sleep 20 # wait 20 ms
  46. mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
  47. sleep 10 # wait 10 ms
  48. mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
  49. sleep 20 # wait 20 ms
  50. mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
  51. sleep 10 # wait 10 ms
  52. mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
  53. sleep 10 # wait 10 ms
  54. # Now run at anything fast... ie: 10mhz!
  55. jtag_khz 10000 # Increase JTAG Speed to 6 MHz
  56. arm7_9 dcc_downloads enable # Enable faster DCC downloads
  57. mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
  58. mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
  59. mww 0xffffec08 0x00160016 # SMC_CYCLE0
  60. mww 0xffffec0c 0x00161003 # SMC_MODE0
  61. flash probe 0 # Identify flash bank 0
  62. mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
  63. mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
  64. mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
  65. mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  66. #mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
  67. mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
  68. mww 0x20000000 0
  69. mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
  70. mww 0x20000000 0
  71. mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  72. mww 0x20000000 0
  73. mww 0xffffea00 0x4
  74. mww 0x20000000 0
  75. mww 0xffffea00 0x4
  76. mww 0x20000000 0
  77. mww 0xffffea00 0x4
  78. mww 0x20000000 0
  79. mww 0xffffea00 0x4
  80. mww 0x20000000 0
  81. mww 0xffffea00 0x4
  82. mww 0x20000000 0
  83. mww 0xffffea00 0x4
  84. mww 0x20000000 0
  85. mww 0xffffea00 0x4
  86. mww 0x20000000 0
  87. mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
  88. mww 0x20000000 0
  89. mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
  90. mww 0x20000000 0
  91. mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
  92. }