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cortex_m3.c 52 KiB

Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>: Some cleanup of the ARMv7-M support: - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and update the Cortex-M3 doc refs (DDI 0337C is no longer available). - Those registers aren't actually general, and some are incorrect (per all public docs anyway). Update comments and code accordingly. * What the Core Debug facility exposes is *implementation-specific* not architectural. These values aren't fully portable. They match Cortex-M3 ... so no current implementation will make trouble, but the next v7m implementation might. * Four of the registers are actually not exposed that way. Before Cortex-M3 r2p0 they are read/written through MRS/MSR instructions. In that newest silicon, they are four bytes in one register, not four separate registers. - Update the CM3 code to report when that one register is available, and not try to access it when it isn't. Also declare the register numbers that an eventual MRS/MSR solution will need to be using. - Stop line wrapping the exception labels. So for parts before r2p0 OpenOCD behavior is effectively unchanged, and still buggy; but for those newer parts a few things might now be correct. Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include most LM3S parts and all STM32 parts. Parts using r2p0 are available, and include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx parts which are now sampling. git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
12 years ago
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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. * *
  26. * *
  27. * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
  28. * *
  29. ***************************************************************************/
  30. #ifdef HAVE_CONFIG_H
  31. #include "config.h"
  32. #endif
  33. #include "cortex_m3.h"
  34. #include "target_request.h"
  35. #include "target_type.h"
  36. #include "arm_disassembler.h"
  37. #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
  38. /* forward declarations */
  39. static int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
  40. static int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
  41. static void cortex_m3_enable_watchpoints(struct target_s *target);
  42. static int cortex_m3_store_core_reg_u32(target_t *target,
  43. enum armv7m_regtype type, uint32_t num, uint32_t value);
  44. #ifdef ARMV7_GDB_HACKS
  45. extern uint8_t armv7m_gdb_dummy_cpsr_value[];
  46. extern reg_t armv7m_gdb_dummy_cpsr_reg;
  47. #endif
  48. static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
  49. uint32_t *value, int regnum)
  50. {
  51. int retval;
  52. uint32_t dcrdr;
  53. /* because the DCB_DCRDR is used for the emulated dcc channel
  54. * we have to save/restore the DCB_DCRDR when used */
  55. mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  56. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  57. /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  58. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  59. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  60. /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  61. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  62. dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  63. retval = swjdp_transaction_endcheck(swjdp);
  64. /* restore DCB_DCRDR - this needs to be in a seperate
  65. * transaction otherwise the emulated DCC channel breaks */
  66. if (retval == ERROR_OK)
  67. retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  68. return retval;
  69. }
  70. static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp,
  71. uint32_t value, int regnum)
  72. {
  73. int retval;
  74. uint32_t dcrdr;
  75. /* because the DCB_DCRDR is used for the emulated dcc channel
  76. * we have to save/restore the DCB_DCRDR when used */
  77. mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  78. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  79. /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
  80. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  81. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  82. /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
  83. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  84. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
  85. retval = swjdp_transaction_endcheck(swjdp);
  86. /* restore DCB_DCRDR - this needs to be in a seperate
  87. * transaction otherwise the emulated DCC channel breaks */
  88. if (retval == ERROR_OK)
  89. retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  90. return retval;
  91. }
  92. static int cortex_m3_write_debug_halt_mask(target_t *target,
  93. uint32_t mask_on, uint32_t mask_off)
  94. {
  95. /* get pointers to arch-specific information */
  96. armv7m_common_t *armv7m = target->arch_info;
  97. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  98. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  99. /* mask off status bits */
  100. cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
  101. /* create new register mask */
  102. cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
  103. return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
  104. }
  105. static int cortex_m3_clear_halt(target_t *target)
  106. {
  107. /* get pointers to arch-specific information */
  108. armv7m_common_t *armv7m = target->arch_info;
  109. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  110. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  111. /* clear step if any */
  112. cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
  113. /* Read Debug Fault Status Register */
  114. mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
  115. /* Clear Debug Fault Status */
  116. mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
  117. LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
  118. return ERROR_OK;
  119. }
  120. static int cortex_m3_single_step_core(target_t *target)
  121. {
  122. /* get pointers to arch-specific information */
  123. armv7m_common_t *armv7m = target->arch_info;
  124. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  125. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  126. uint32_t dhcsr_save;
  127. /* backup dhcsr reg */
  128. dhcsr_save = cortex_m3->dcb_dhcsr;
  129. /* mask interrupts if not done already */
  130. if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
  131. mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
  132. mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
  133. LOG_DEBUG(" ");
  134. /* restore dhcsr reg */
  135. cortex_m3->dcb_dhcsr = dhcsr_save;
  136. cortex_m3_clear_halt(target);
  137. return ERROR_OK;
  138. }
  139. static int cortex_m3_endreset_event(target_t *target)
  140. {
  141. int i;
  142. uint32_t dcb_demcr;
  143. /* get pointers to arch-specific information */
  144. armv7m_common_t *armv7m = target->arch_info;
  145. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  146. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  147. cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
  148. cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
  149. mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
  150. LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
  151. /* this regsiter is used for emulated dcc channel */
  152. mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
  153. /* Enable debug requests */
  154. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  155. if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
  156. mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
  157. /* clear any interrupt masking */
  158. cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
  159. /* Enable trace and dwt */
  160. mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
  161. /* Monitor bus faults */
  162. mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
  163. /* Enable FPB */
  164. target_write_u32(target, FP_CTRL, 3);
  165. cortex_m3->fpb_enabled = 1;
  166. /* Restore FPB registers */
  167. for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
  168. {
  169. target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
  170. }
  171. /* Restore DWT registers */
  172. for (i = 0; i < cortex_m3->dwt_num_comp; i++)
  173. {
  174. target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp);
  175. target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask);
  176. target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function);
  177. }
  178. swjdp_transaction_endcheck(swjdp);
  179. armv7m_invalidate_core_regs(target);
  180. /* make sure we have latest dhcsr flags */
  181. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  182. return ERROR_OK;
  183. }
  184. static int cortex_m3_examine_debug_reason(target_t *target)
  185. {
  186. /* get pointers to arch-specific information */
  187. armv7m_common_t *armv7m = target->arch_info;
  188. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  189. /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
  190. /* only check the debug reason if we don't know it already */
  191. if ((target->debug_reason != DBG_REASON_DBGRQ)
  192. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  193. {
  194. if (cortex_m3->nvic_dfsr & DFSR_BKPT)
  195. {
  196. target->debug_reason = DBG_REASON_BREAKPOINT;
  197. if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
  198. target->debug_reason = DBG_REASON_WPTANDBKPT;
  199. }
  200. else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
  201. target->debug_reason = DBG_REASON_WATCHPOINT;
  202. else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
  203. target->debug_reason = DBG_REASON_BREAKPOINT;
  204. else /* EXTERNAL, HALTED, DWTTRAP w/o BKPT */
  205. target->debug_reason = DBG_REASON_UNDEFINED;
  206. }
  207. return ERROR_OK;
  208. }
  209. static int cortex_m3_examine_exception_reason(target_t *target)
  210. {
  211. uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
  212. /* get pointers to arch-specific information */
  213. armv7m_common_t *armv7m = target->arch_info;
  214. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  215. mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
  216. switch (armv7m->exception_number)
  217. {
  218. case 2: /* NMI */
  219. break;
  220. case 3: /* Hard Fault */
  221. mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
  222. if (except_sr & 0x40000000)
  223. {
  224. mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
  225. }
  226. break;
  227. case 4: /* Memory Management */
  228. mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  229. mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
  230. break;
  231. case 5: /* Bus Fault */
  232. mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  233. mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
  234. break;
  235. case 6: /* Usage Fault */
  236. mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  237. break;
  238. case 11: /* SVCall */
  239. break;
  240. case 12: /* Debug Monitor */
  241. mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
  242. break;
  243. case 14: /* PendSV */
  244. break;
  245. case 15: /* SysTick */
  246. break;
  247. default:
  248. except_sr = 0;
  249. break;
  250. }
  251. swjdp_transaction_endcheck(swjdp);
  252. LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
  253. shcsr, except_sr, cfsr, except_ar);
  254. return ERROR_OK;
  255. }
  256. static int cortex_m3_debug_entry(target_t *target)
  257. {
  258. int i;
  259. uint32_t xPSR;
  260. int retval;
  261. /* get pointers to arch-specific information */
  262. armv7m_common_t *armv7m = target->arch_info;
  263. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  264. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  265. LOG_DEBUG(" ");
  266. if (armv7m->pre_debug_entry)
  267. armv7m->pre_debug_entry(target);
  268. cortex_m3_clear_halt(target);
  269. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  270. if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
  271. return retval;
  272. /* Examine target state and mode */
  273. /* First load register acessible through core debug port*/
  274. int num_regs = armv7m->core_cache->num_regs;
  275. for (i = 0; i < num_regs; i++)
  276. {
  277. if (!armv7m->core_cache->reg_list[i].valid)
  278. armv7m->read_core_reg(target, i);
  279. }
  280. xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
  281. #ifdef ARMV7_GDB_HACKS
  282. /* copy real xpsr reg for gdb, setting thumb bit */
  283. buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
  284. buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
  285. armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
  286. armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
  287. #endif
  288. /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
  289. if (xPSR & 0xf00)
  290. {
  291. armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
  292. cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
  293. }
  294. /* Are we in an exception handler */
  295. if (xPSR & 0x1FF)
  296. {
  297. armv7m->core_mode = ARMV7M_MODE_HANDLER;
  298. armv7m->exception_number = (xPSR & 0x1FF);
  299. }
  300. else
  301. {
  302. armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
  303. armv7m->exception_number = 0;
  304. }
  305. if (armv7m->exception_number)
  306. {
  307. cortex_m3_examine_exception_reason(target);
  308. }
  309. LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
  310. armv7m_mode_strings[armv7m->core_mode],
  311. *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
  312. target_state_name(target));
  313. if (armv7m->post_debug_entry)
  314. armv7m->post_debug_entry(target);
  315. return ERROR_OK;
  316. }
  317. static int cortex_m3_poll(target_t *target)
  318. {
  319. int retval;
  320. enum target_state prev_target_state = target->state;
  321. /* get pointers to arch-specific information */
  322. armv7m_common_t *armv7m = target->arch_info;
  323. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  324. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  325. /* Read from Debug Halting Control and Status Register */
  326. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  327. if (retval != ERROR_OK)
  328. {
  329. target->state = TARGET_UNKNOWN;
  330. return retval;
  331. }
  332. if (cortex_m3->dcb_dhcsr & S_RESET_ST)
  333. {
  334. /* check if still in reset */
  335. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  336. if (cortex_m3->dcb_dhcsr & S_RESET_ST)
  337. {
  338. target->state = TARGET_RESET;
  339. return ERROR_OK;
  340. }
  341. }
  342. if (target->state == TARGET_RESET)
  343. {
  344. /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
  345. LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
  346. cortex_m3_endreset_event(target);
  347. target->state = TARGET_RUNNING;
  348. prev_target_state = TARGET_RUNNING;
  349. }
  350. if (cortex_m3->dcb_dhcsr & S_HALT)
  351. {
  352. target->state = TARGET_HALTED;
  353. if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
  354. {
  355. if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
  356. return retval;
  357. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  358. }
  359. if (prev_target_state == TARGET_DEBUG_RUNNING)
  360. {
  361. LOG_DEBUG(" ");
  362. if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
  363. return retval;
  364. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  365. }
  366. }
  367. /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
  368. * How best to model low power modes?
  369. */
  370. if (target->state == TARGET_UNKNOWN)
  371. {
  372. /* check if processor is retiring instructions */
  373. if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
  374. {
  375. target->state = TARGET_RUNNING;
  376. return ERROR_OK;
  377. }
  378. }
  379. return ERROR_OK;
  380. }
  381. static int cortex_m3_halt(target_t *target)
  382. {
  383. LOG_DEBUG("target->state: %s",
  384. target_state_name(target));
  385. if (target->state == TARGET_HALTED)
  386. {
  387. LOG_DEBUG("target was already halted");
  388. return ERROR_OK;
  389. }
  390. if (target->state == TARGET_UNKNOWN)
  391. {
  392. LOG_WARNING("target was in unknown state when halt was requested");
  393. }
  394. if (target->state == TARGET_RESET)
  395. {
  396. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
  397. {
  398. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  399. return ERROR_TARGET_FAILURE;
  400. }
  401. else
  402. {
  403. /* we came here in a reset_halt or reset_init sequence
  404. * debug entry was already prepared in cortex_m3_prepare_reset_halt()
  405. */
  406. target->debug_reason = DBG_REASON_DBGRQ;
  407. return ERROR_OK;
  408. }
  409. }
  410. /* Write to Debug Halting Control and Status Register */
  411. cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
  412. target->debug_reason = DBG_REASON_DBGRQ;
  413. return ERROR_OK;
  414. }
  415. static int cortex_m3_soft_reset_halt(struct target_s *target)
  416. {
  417. /* get pointers to arch-specific information */
  418. armv7m_common_t *armv7m = target->arch_info;
  419. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  420. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  421. uint32_t dcb_dhcsr = 0;
  422. int retval, timeout = 0;
  423. /* Enter debug state on reset, cf. end_reset_event() */
  424. mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
  425. /* Request a reset */
  426. mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
  427. target->state = TARGET_RESET;
  428. /* registers are now invalid */
  429. armv7m_invalidate_core_regs(target);
  430. while (timeout < 100)
  431. {
  432. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
  433. if (retval == ERROR_OK)
  434. {
  435. mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
  436. if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
  437. {
  438. LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
  439. cortex_m3_poll(target);
  440. return ERROR_OK;
  441. }
  442. else
  443. LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
  444. }
  445. timeout++;
  446. alive_sleep(1);
  447. }
  448. return ERROR_OK;
  449. }
  450. static void cortex_m3_enable_breakpoints(struct target_s *target)
  451. {
  452. breakpoint_t *breakpoint = target->breakpoints;
  453. /* set any pending breakpoints */
  454. while (breakpoint)
  455. {
  456. if (breakpoint->set == 0)
  457. cortex_m3_set_breakpoint(target, breakpoint);
  458. breakpoint = breakpoint->next;
  459. }
  460. }
  461. static int cortex_m3_resume(struct target_s *target, int current,
  462. uint32_t address, int handle_breakpoints, int debug_execution)
  463. {
  464. /* get pointers to arch-specific information */
  465. armv7m_common_t *armv7m = target->arch_info;
  466. breakpoint_t *breakpoint = NULL;
  467. uint32_t resume_pc;
  468. if (target->state != TARGET_HALTED)
  469. {
  470. LOG_WARNING("target not halted");
  471. return ERROR_TARGET_NOT_HALTED;
  472. }
  473. if (!debug_execution)
  474. {
  475. target_free_all_working_areas(target);
  476. cortex_m3_enable_breakpoints(target);
  477. cortex_m3_enable_watchpoints(target);
  478. }
  479. if (debug_execution)
  480. {
  481. /* Disable interrupts */
  482. /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
  483. * This is probably the same issue as Cortex-M3 Errata 377493:
  484. * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
  485. buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
  486. armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
  487. armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
  488. /* Make sure we are in Thumb mode */
  489. buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
  490. buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
  491. armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
  492. armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
  493. }
  494. /* current = 1: continue on current pc, otherwise continue at <address> */
  495. if (!current)
  496. {
  497. buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
  498. armv7m->core_cache->reg_list[15].dirty = 1;
  499. armv7m->core_cache->reg_list[15].valid = 1;
  500. }
  501. resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
  502. armv7m_restore_context(target);
  503. /* the front-end may request us not to handle breakpoints */
  504. if (handle_breakpoints)
  505. {
  506. /* Single step past breakpoint at current address */
  507. if ((breakpoint = breakpoint_find(target, resume_pc)))
  508. {
  509. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
  510. breakpoint->address,
  511. breakpoint->unique_id );
  512. cortex_m3_unset_breakpoint(target, breakpoint);
  513. cortex_m3_single_step_core(target);
  514. cortex_m3_set_breakpoint(target, breakpoint);
  515. }
  516. }
  517. /* Restart core */
  518. cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
  519. target->debug_reason = DBG_REASON_NOTHALTED;
  520. /* registers are now invalid */
  521. armv7m_invalidate_core_regs(target);
  522. if (!debug_execution)
  523. {
  524. target->state = TARGET_RUNNING;
  525. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  526. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  527. }
  528. else
  529. {
  530. target->state = TARGET_DEBUG_RUNNING;
  531. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  532. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  533. }
  534. return ERROR_OK;
  535. }
  536. /* int irqstepcount = 0; */
  537. static int cortex_m3_step(struct target_s *target, int current,
  538. uint32_t address, int handle_breakpoints)
  539. {
  540. /* get pointers to arch-specific information */
  541. armv7m_common_t *armv7m = target->arch_info;
  542. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  543. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  544. breakpoint_t *breakpoint = NULL;
  545. if (target->state != TARGET_HALTED)
  546. {
  547. LOG_WARNING("target not halted");
  548. return ERROR_TARGET_NOT_HALTED;
  549. }
  550. /* current = 1: continue on current pc, otherwise continue at <address> */
  551. if (!current)
  552. buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
  553. /* the front-end may request us not to handle breakpoints */
  554. if (handle_breakpoints)
  555. if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32))))
  556. cortex_m3_unset_breakpoint(target, breakpoint);
  557. target->debug_reason = DBG_REASON_SINGLESTEP;
  558. armv7m_restore_context(target);
  559. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  560. /* set step and clear halt */
  561. cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
  562. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  563. /* registers are now invalid */
  564. armv7m_invalidate_core_regs(target);
  565. if (breakpoint)
  566. cortex_m3_set_breakpoint(target, breakpoint);
  567. LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
  568. cortex_m3_debug_entry(target);
  569. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  570. LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
  571. return ERROR_OK;
  572. }
  573. static int cortex_m3_assert_reset(target_t *target)
  574. {
  575. armv7m_common_t *armv7m = target->arch_info;
  576. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  577. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  578. int assert_srst = 1;
  579. LOG_DEBUG("target->state: %s",
  580. target_state_name(target));
  581. enum reset_types jtag_reset_config = jtag_get_reset_config();
  582. /*
  583. * We can reset Cortex-M3 targets using just the NVIC without
  584. * requiring SRST, getting a SoC reset (or a core-only reset)
  585. * instead of a system reset.
  586. */
  587. if (!(jtag_reset_config & RESET_HAS_SRST))
  588. assert_srst = 0;
  589. /* Enable debug requests */
  590. mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  591. if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
  592. mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
  593. mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
  594. if (!target->reset_halt)
  595. {
  596. /* Set/Clear C_MASKINTS in a separate operation */
  597. if (cortex_m3->dcb_dhcsr & C_MASKINTS)
  598. mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
  599. /* clear any debug flags before resuming */
  600. cortex_m3_clear_halt(target);
  601. /* clear C_HALT in dhcsr reg */
  602. cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
  603. /* Enter debug state on reset, cf. end_reset_event() */
  604. mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
  605. }
  606. else
  607. {
  608. /* Enter debug state on reset, cf. end_reset_event() */
  609. mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
  610. }
  611. /*
  612. * When nRST is asserted on most Stellaris devices, it clears some of
  613. * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
  614. * and OpenOCD depends on those TRMs. So we won't use SRST on those
  615. * chips. (Only power-on reset should affect debug state, beyond a
  616. * few specified bits; not the chip's nRST input, wired to SRST.)
  617. *
  618. * REVISIT current errata specs don't seem to cover this issue.
  619. * Do we have more details than this email?
  620. * https://lists.berlios.de/pipermail
  621. * /openocd-development/2008-August/003065.html
  622. */
  623. if (strcmp(target->variant, "lm3s") == 0)
  624. {
  625. /* Check for silicon revisions with the issue. */
  626. uint32_t did0;
  627. if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
  628. {
  629. switch ((did0 >> 16) & 0xff)
  630. {
  631. case 0:
  632. /* all Sandstorm suffer issue */
  633. assert_srst = 0;
  634. break;
  635. case 1:
  636. case 3:
  637. /* Fury and DustDevil rev A have
  638. * this nRST problem. It should
  639. * be fixed in rev B silicon.
  640. */
  641. if (((did0 >> 8) & 0xff) == 0)
  642. assert_srst = 0;
  643. break;
  644. case 4:
  645. /* Tempest should be fine. */
  646. break;
  647. }
  648. }
  649. }
  650. if (assert_srst)
  651. {
  652. /* default to asserting srst */
  653. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  654. {
  655. jtag_add_reset(1, 1);
  656. }
  657. else
  658. {
  659. jtag_add_reset(0, 1);
  660. }
  661. }
  662. else
  663. {
  664. /* Use a standard Cortex-M3 software reset mechanism.
  665. * SYSRESETREQ will reset SoC peripherals outside the
  666. * core, like watchdog timers, if the SoC wires it up
  667. * correctly. Else VECRESET can reset just the core.
  668. */
  669. mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
  670. AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
  671. LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
  672. {
  673. /* I do not know why this is necessary, but it
  674. * fixes strange effects (step/resume cause NMI
  675. * after reset) on LM3S6918 -- Michael Schwingen
  676. */
  677. uint32_t tmp;
  678. mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
  679. }
  680. }
  681. target->state = TARGET_RESET;
  682. jtag_add_sleep(50000);
  683. armv7m_invalidate_core_regs(target);
  684. if (target->reset_halt)
  685. {
  686. int retval;
  687. if ((retval = target_halt(target)) != ERROR_OK)
  688. return retval;
  689. }
  690. return ERROR_OK;
  691. }
  692. static int cortex_m3_deassert_reset(target_t *target)
  693. {
  694. LOG_DEBUG("target->state: %s",
  695. target_state_name(target));
  696. /* deassert reset lines */
  697. jtag_add_reset(0, 0);
  698. return ERROR_OK;
  699. }
  700. static int
  701. cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  702. {
  703. int retval;
  704. int fp_num = 0;
  705. uint32_t hilo;
  706. /* get pointers to arch-specific information */
  707. armv7m_common_t *armv7m = target->arch_info;
  708. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  709. cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
  710. if (breakpoint->set)
  711. {
  712. LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
  713. return ERROR_OK;
  714. }
  715. if (cortex_m3->auto_bp_type)
  716. {
  717. breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
  718. }
  719. if (breakpoint->type == BKPT_HARD)
  720. {
  721. while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
  722. fp_num++;
  723. if (fp_num >= cortex_m3->fp_num_code)
  724. {
  725. LOG_DEBUG("ERROR Can not find free FP Comparator");
  726. LOG_WARNING("ERROR Can not find free FP Comparator");
  727. exit(-1);
  728. }
  729. breakpoint->set = fp_num + 1;
  730. hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
  731. comparator_list[fp_num].used = 1;
  732. comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
  733. target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
  734. LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
  735. if (!cortex_m3->fpb_enabled)
  736. {
  737. LOG_DEBUG("FPB wasn't enabled, do it now");
  738. target_write_u32(target, FP_CTRL, 3);
  739. }
  740. }
  741. else if (breakpoint->type == BKPT_SOFT)
  742. {
  743. uint8_t code[4];
  744. buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
  745. if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
  746. {
  747. return retval;
  748. }
  749. if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
  750. {
  751. return retval;
  752. }
  753. breakpoint->set = 0x11; /* Any nice value but 0 */
  754. }
  755. LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
  756. breakpoint->unique_id,
  757. (int)(breakpoint->type),
  758. breakpoint->address,
  759. breakpoint->length,
  760. breakpoint->set);
  761. return ERROR_OK;
  762. }
  763. static int
  764. cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  765. {
  766. int retval;
  767. /* get pointers to arch-specific information */
  768. armv7m_common_t *armv7m = target->arch_info;
  769. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  770. cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
  771. if (!breakpoint->set)
  772. {
  773. LOG_WARNING("breakpoint not set");
  774. return ERROR_OK;
  775. }
  776. LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
  777. breakpoint->unique_id,
  778. (int)(breakpoint->type),
  779. breakpoint->address,
  780. breakpoint->length,
  781. breakpoint->set);
  782. if (breakpoint->type == BKPT_HARD)
  783. {
  784. int fp_num = breakpoint->set - 1;
  785. if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
  786. {
  787. LOG_DEBUG("Invalid FP Comparator number in breakpoint");
  788. return ERROR_OK;
  789. }
  790. comparator_list[fp_num].used = 0;
  791. comparator_list[fp_num].fpcr_value = 0;
  792. target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
  793. }
  794. else
  795. {
  796. /* restore original instruction (kept in target endianness) */
  797. if (breakpoint->length == 4)
  798. {
  799. if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  800. {
  801. return retval;
  802. }
  803. }
  804. else
  805. {
  806. if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  807. {
  808. return retval;
  809. }
  810. }
  811. }
  812. breakpoint->set = 0;
  813. return ERROR_OK;
  814. }
  815. static int
  816. cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  817. {
  818. /* get pointers to arch-specific information */
  819. armv7m_common_t *armv7m = target->arch_info;
  820. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  821. if (cortex_m3->auto_bp_type)
  822. {
  823. breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
  824. #ifdef ARMV7_GDB_HACKS
  825. if (breakpoint->length != 2) {
  826. /* XXX Hack: Replace all breakpoints with length != 2 with
  827. * a hardware breakpoint. */
  828. breakpoint->type = BKPT_HARD;
  829. breakpoint->length = 2;
  830. }
  831. #endif
  832. }
  833. if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
  834. {
  835. LOG_INFO("flash patch comparator requested outside code memory region");
  836. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  837. }
  838. if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
  839. {
  840. LOG_INFO("soft breakpoint requested in code (flash) memory region");
  841. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  842. }
  843. if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
  844. {
  845. LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
  846. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  847. }
  848. if ((breakpoint->length != 2))
  849. {
  850. LOG_INFO("only breakpoints of two bytes length supported");
  851. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  852. }
  853. if (breakpoint->type == BKPT_HARD)
  854. cortex_m3->fp_code_available--;
  855. cortex_m3_set_breakpoint(target, breakpoint);
  856. return ERROR_OK;
  857. }
  858. static int
  859. cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  860. {
  861. /* get pointers to arch-specific information */
  862. armv7m_common_t *armv7m = target->arch_info;
  863. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  864. if (target->state != TARGET_HALTED)
  865. {
  866. LOG_WARNING("target not halted");
  867. return ERROR_TARGET_NOT_HALTED;
  868. }
  869. if (cortex_m3->auto_bp_type)
  870. {
  871. breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
  872. }
  873. if (breakpoint->set)
  874. {
  875. cortex_m3_unset_breakpoint(target, breakpoint);
  876. }
  877. if (breakpoint->type == BKPT_HARD)
  878. cortex_m3->fp_code_available++;
  879. return ERROR_OK;
  880. }
  881. static int
  882. cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  883. {
  884. int dwt_num = 0;
  885. uint32_t mask, temp;
  886. /* get pointers to arch-specific information */
  887. armv7m_common_t *armv7m = target->arch_info;
  888. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  889. cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list;
  890. if (watchpoint->set)
  891. {
  892. LOG_WARNING("watchpoint (%d) already set", watchpoint->unique_id );
  893. return ERROR_OK;
  894. }
  895. if (watchpoint->mask == 0xffffffffu)
  896. {
  897. while (comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp))
  898. dwt_num++;
  899. if (dwt_num >= cortex_m3->dwt_num_comp)
  900. {
  901. LOG_DEBUG("ERROR Can not find free DWT Comparator");
  902. LOG_WARNING("ERROR Can not find free DWT Comparator");
  903. return -1;
  904. }
  905. watchpoint->set = dwt_num + 1;
  906. mask = 0;
  907. temp = watchpoint->length;
  908. while (temp > 1)
  909. {
  910. temp = temp / 2;
  911. mask++;
  912. }
  913. comparator_list[dwt_num].used = 1;
  914. comparator_list[dwt_num].comp = watchpoint->address;
  915. comparator_list[dwt_num].mask = mask;
  916. comparator_list[dwt_num].function = watchpoint->rw + 5;
  917. target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
  918. target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x4, comparator_list[dwt_num].mask);
  919. target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
  920. LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
  921. }
  922. else
  923. {
  924. /* Move this test to add_watchpoint */
  925. LOG_WARNING("Cannot watch data values (id: %d)",
  926. watchpoint->unique_id );
  927. return ERROR_OK;
  928. }
  929. LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ",
  930. watchpoint->unique_id, watchpoint->address, watchpoint->set );
  931. return ERROR_OK;
  932. }
  933. static int
  934. cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  935. {
  936. /* get pointers to arch-specific information */
  937. armv7m_common_t *armv7m = target->arch_info;
  938. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  939. cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list;
  940. int dwt_num;
  941. if (!watchpoint->set)
  942. {
  943. LOG_WARNING("watchpoint (wpid: %d) not set", watchpoint->unique_id );
  944. return ERROR_OK;
  945. }
  946. LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ",
  947. watchpoint->unique_id, watchpoint->address,watchpoint->set );
  948. dwt_num = watchpoint->set - 1;
  949. if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
  950. {
  951. LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
  952. return ERROR_OK;
  953. }
  954. comparator_list[dwt_num].used = 0;
  955. comparator_list[dwt_num].function = 0;
  956. target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
  957. watchpoint->set = 0;
  958. return ERROR_OK;
  959. }
  960. static int
  961. cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  962. {
  963. /* get pointers to arch-specific information */
  964. armv7m_common_t *armv7m = target->arch_info;
  965. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  966. if (target->state != TARGET_HALTED)
  967. {
  968. LOG_WARNING("target not halted");
  969. return ERROR_TARGET_NOT_HALTED;
  970. }
  971. if (cortex_m3->dwt_comp_available < 1)
  972. {
  973. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  974. }
  975. if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
  976. {
  977. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  978. }
  979. cortex_m3->dwt_comp_available--;
  980. LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
  981. return ERROR_OK;
  982. }
  983. static int
  984. cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  985. {
  986. /* get pointers to arch-specific information */
  987. armv7m_common_t *armv7m = target->arch_info;
  988. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  989. if (target->state != TARGET_HALTED)
  990. {
  991. LOG_WARNING("target not halted");
  992. return ERROR_TARGET_NOT_HALTED;
  993. }
  994. if (watchpoint->set)
  995. {
  996. cortex_m3_unset_watchpoint(target, watchpoint);
  997. }
  998. cortex_m3->dwt_comp_available++;
  999. LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
  1000. return ERROR_OK;
  1001. }
  1002. static void cortex_m3_enable_watchpoints(struct target_s *target)
  1003. {
  1004. watchpoint_t *watchpoint = target->watchpoints;
  1005. /* set any pending watchpoints */
  1006. while (watchpoint)
  1007. {
  1008. if (watchpoint->set == 0)
  1009. cortex_m3_set_watchpoint(target, watchpoint);
  1010. watchpoint = watchpoint->next;
  1011. }
  1012. }
  1013. static int cortex_m3_load_core_reg_u32(struct target_s *target,
  1014. enum armv7m_regtype type, uint32_t num, uint32_t * value)
  1015. {
  1016. int retval;
  1017. /* get pointers to arch-specific information */
  1018. armv7m_common_t *armv7m = target->arch_info;
  1019. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1020. /* NOTE: we "know" here that the register identifiers used
  1021. * in the v7m header match the Cortex-M3 Debug Core Register
  1022. * Selector values for R0..R15, xPSR, MSP, and PSP.
  1023. */
  1024. switch (num) {
  1025. case 0 ... 18:
  1026. /* read a normal core register */
  1027. retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
  1028. if (retval != ERROR_OK)
  1029. {
  1030. LOG_ERROR("JTAG failure %i",retval);
  1031. return ERROR_JTAG_DEVICE_ERROR;
  1032. }
  1033. LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
  1034. break;
  1035. case ARMV7M_PRIMASK:
  1036. case ARMV7M_BASEPRI:
  1037. case ARMV7M_FAULTMASK:
  1038. case ARMV7M_CONTROL:
  1039. /* Cortex-M3 packages these four registers as bitfields
  1040. * in one Debug Core register. So say r0 and r2 docs;
  1041. * it was removed from r1 docs, but still works.
  1042. */
  1043. cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
  1044. switch (num)
  1045. {
  1046. case ARMV7M_PRIMASK:
  1047. *value = buf_get_u32((uint8_t*)value, 0, 1);
  1048. break;
  1049. case ARMV7M_BASEPRI:
  1050. *value = buf_get_u32((uint8_t*)value, 8, 8);
  1051. break;
  1052. case ARMV7M_FAULTMASK:
  1053. *value = buf_get_u32((uint8_t*)value, 16, 1);
  1054. break;
  1055. case ARMV7M_CONTROL:
  1056. *value = buf_get_u32((uint8_t*)value, 24, 2);
  1057. break;
  1058. }
  1059. LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
  1060. break;
  1061. default:
  1062. return ERROR_INVALID_ARGUMENTS;
  1063. }
  1064. return ERROR_OK;
  1065. }
  1066. static int cortex_m3_store_core_reg_u32(struct target_s *target,
  1067. enum armv7m_regtype type, uint32_t num, uint32_t value)
  1068. {
  1069. int retval;
  1070. uint32_t reg;
  1071. /* get pointers to arch-specific information */
  1072. armv7m_common_t *armv7m = target->arch_info;
  1073. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1074. #ifdef ARMV7_GDB_HACKS
  1075. /* If the LR register is being modified, make sure it will put us
  1076. * in "thumb" mode, or an INVSTATE exception will occur. This is a
  1077. * hack to deal with the fact that gdb will sometimes "forge"
  1078. * return addresses, and doesn't set the LSB correctly (i.e., when
  1079. * printing expressions containing function calls, it sets LR = 0.)
  1080. * Valid exception return codes have bit 0 set too.
  1081. */
  1082. if (num == ARMV7M_R14)
  1083. value |= 0x01;
  1084. #endif
  1085. /* NOTE: we "know" here that the register identifiers used
  1086. * in the v7m header match the Cortex-M3 Debug Core Register
  1087. * Selector values for R0..R15, xPSR, MSP, and PSP.
  1088. */
  1089. switch (num) {
  1090. case 0 ... 18:
  1091. retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
  1092. if (retval != ERROR_OK)
  1093. {
  1094. LOG_ERROR("JTAG failure %i", retval);
  1095. armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
  1096. return ERROR_JTAG_DEVICE_ERROR;
  1097. }
  1098. LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
  1099. break;
  1100. case ARMV7M_PRIMASK:
  1101. case ARMV7M_BASEPRI:
  1102. case ARMV7M_FAULTMASK:
  1103. case ARMV7M_CONTROL:
  1104. /* Cortex-M3 packages these four registers as bitfields
  1105. * in one Debug Core register. So say r0 and r2 docs;
  1106. * it was removed from r1 docs, but still works.
  1107. */
  1108. cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
  1109. switch (num)
  1110. {
  1111. case ARMV7M_PRIMASK:
  1112. buf_set_u32((uint8_t*)&reg, 0, 1, value);
  1113. break;
  1114. case ARMV7M_BASEPRI:
  1115. buf_set_u32((uint8_t*)&reg, 8, 8, value);
  1116. break;
  1117. case ARMV7M_FAULTMASK:
  1118. buf_set_u32((uint8_t*)&reg, 16, 1, value);
  1119. break;
  1120. case ARMV7M_CONTROL:
  1121. buf_set_u32((uint8_t*)&reg, 24, 2, value);
  1122. break;
  1123. }
  1124. cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
  1125. LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
  1126. break;
  1127. default:
  1128. return ERROR_INVALID_ARGUMENTS;
  1129. }
  1130. return ERROR_OK;
  1131. }
  1132. static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
  1133. uint32_t size, uint32_t count, uint8_t *buffer)
  1134. {
  1135. /* get pointers to arch-specific information */
  1136. armv7m_common_t *armv7m = target->arch_info;
  1137. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1138. int retval;
  1139. /* sanitize arguments */
  1140. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1141. return ERROR_INVALID_ARGUMENTS;
  1142. /* cortex_m3 handles unaligned memory access */
  1143. switch (size)
  1144. {
  1145. case 4:
  1146. retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
  1147. break;
  1148. case 2:
  1149. retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
  1150. break;
  1151. case 1:
  1152. retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
  1153. break;
  1154. default:
  1155. LOG_ERROR("BUG: we shouldn't get here");
  1156. exit(-1);
  1157. }
  1158. return retval;
  1159. }
  1160. static int cortex_m3_write_memory(struct target_s *target, uint32_t address,
  1161. uint32_t size, uint32_t count, uint8_t *buffer)
  1162. {
  1163. /* get pointers to arch-specific information */
  1164. armv7m_common_t *armv7m = target->arch_info;
  1165. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1166. int retval;
  1167. /* sanitize arguments */
  1168. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1169. return ERROR_INVALID_ARGUMENTS;
  1170. switch (size)
  1171. {
  1172. case 4:
  1173. retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
  1174. break;
  1175. case 2:
  1176. retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
  1177. break;
  1178. case 1:
  1179. retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
  1180. break;
  1181. default:
  1182. LOG_ERROR("BUG: we shouldn't get here");
  1183. exit(-1);
  1184. }
  1185. return retval;
  1186. }
  1187. static int cortex_m3_bulk_write_memory(target_t *target, uint32_t address,
  1188. uint32_t count, uint8_t *buffer)
  1189. {
  1190. return cortex_m3_write_memory(target, address, 4, count, buffer);
  1191. }
  1192. static void cortex_m3_build_reg_cache(target_t *target)
  1193. {
  1194. armv7m_build_reg_cache(target);
  1195. }
  1196. static int cortex_m3_init_target(struct command_context_s *cmd_ctx,
  1197. struct target_s *target)
  1198. {
  1199. cortex_m3_build_reg_cache(target);
  1200. return ERROR_OK;
  1201. }
  1202. static int cortex_m3_examine(struct target_s *target)
  1203. {
  1204. int retval;
  1205. uint32_t cpuid, fpcr, dwtcr, ictr;
  1206. int i;
  1207. /* get pointers to arch-specific information */
  1208. armv7m_common_t *armv7m = target->arch_info;
  1209. cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
  1210. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1211. if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
  1212. return retval;
  1213. if (!target_was_examined(target))
  1214. {
  1215. target_set_examined(target);
  1216. /* Read from Device Identification Registers */
  1217. if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK)
  1218. return retval;
  1219. if (((cpuid >> 4) & 0xc3f) == 0xc23)
  1220. LOG_DEBUG("CORTEX-M3 processor detected");
  1221. LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
  1222. target_read_u32(target, NVIC_ICTR, &ictr);
  1223. cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
  1224. cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4);
  1225. for (i = 0; i < cortex_m3->intlinesnum; i++)
  1226. {
  1227. target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
  1228. LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]);
  1229. }
  1230. /* Setup FPB */
  1231. target_read_u32(target, FP_CTRL, &fpcr);
  1232. cortex_m3->auto_bp_type = 1;
  1233. cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
  1234. cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
  1235. cortex_m3->fp_code_available = cortex_m3->fp_num_code;
  1236. cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
  1237. cortex_m3->fpb_enabled = fpcr & 1;
  1238. for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
  1239. {
  1240. cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
  1241. cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
  1242. }
  1243. LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
  1244. /* Setup DWT */
  1245. target_read_u32(target, DWT_CTRL, &dwtcr);
  1246. cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF;
  1247. cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp;
  1248. cortex_m3->dwt_comparator_list = calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t));
  1249. for (i = 0; i < cortex_m3->dwt_num_comp; i++)
  1250. {
  1251. cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i;
  1252. }
  1253. }
  1254. return ERROR_OK;
  1255. }
  1256. static int cortex_m3_quit(void)
  1257. {
  1258. return ERROR_OK;
  1259. }
  1260. static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
  1261. {
  1262. uint16_t dcrdr;
  1263. mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
  1264. *ctrl = (uint8_t)dcrdr;
  1265. *value = (uint8_t)(dcrdr >> 8);
  1266. LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
  1267. /* write ack back to software dcc register
  1268. * signify we have read data */
  1269. if (dcrdr & (1 << 0))
  1270. {
  1271. dcrdr = 0;
  1272. mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
  1273. }
  1274. return ERROR_OK;
  1275. }
  1276. static int cortex_m3_target_request_data(target_t *target,
  1277. uint32_t size, uint8_t *buffer)
  1278. {
  1279. armv7m_common_t *armv7m = target->arch_info;
  1280. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1281. uint8_t data;
  1282. uint8_t ctrl;
  1283. uint32_t i;
  1284. for (i = 0; i < (size * 4); i++)
  1285. {
  1286. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1287. buffer[i] = data;
  1288. }
  1289. return ERROR_OK;
  1290. }
  1291. static int cortex_m3_handle_target_request(void *priv)
  1292. {
  1293. target_t *target = priv;
  1294. if (!target_was_examined(target))
  1295. return ERROR_OK;
  1296. armv7m_common_t *armv7m = target->arch_info;
  1297. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1298. if (!target->dbg_msg_enabled)
  1299. return ERROR_OK;
  1300. if (target->state == TARGET_RUNNING)
  1301. {
  1302. uint8_t data;
  1303. uint8_t ctrl;
  1304. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1305. /* check if we have data */
  1306. if (ctrl & (1 << 0))
  1307. {
  1308. uint32_t request;
  1309. /* we assume target is quick enough */
  1310. request = data;
  1311. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1312. request |= (data << 8);
  1313. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1314. request |= (data << 16);
  1315. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1316. request |= (data << 24);
  1317. target_request(target, request);
  1318. }
  1319. }
  1320. return ERROR_OK;
  1321. }
  1322. static int cortex_m3_init_arch_info(target_t *target,
  1323. cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
  1324. {
  1325. int retval;
  1326. armv7m_common_t *armv7m;
  1327. armv7m = &cortex_m3->armv7m;
  1328. armv7m_init_arch_info(target, armv7m);
  1329. /* prepare JTAG information for the new target */
  1330. cortex_m3->jtag_info.tap = tap;
  1331. cortex_m3->jtag_info.scann_size = 4;
  1332. armv7m->swjdp_info.dp_select_value = -1;
  1333. armv7m->swjdp_info.ap_csw_value = -1;
  1334. armv7m->swjdp_info.ap_tar_value = -1;
  1335. armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
  1336. armv7m->swjdp_info.memaccess_tck = 8;
  1337. armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
  1338. /* initialize arch-specific breakpoint handling */
  1339. cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
  1340. cortex_m3->arch_info = NULL;
  1341. /* register arch-specific functions */
  1342. armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
  1343. armv7m->pre_debug_entry = NULL;
  1344. armv7m->post_debug_entry = NULL;
  1345. armv7m->pre_restore_context = NULL;
  1346. armv7m->post_restore_context = NULL;
  1347. armv7m->arch_info = cortex_m3;
  1348. armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
  1349. armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
  1350. target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
  1351. if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
  1352. {
  1353. return retval;
  1354. }
  1355. return ERROR_OK;
  1356. }
  1357. static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
  1358. {
  1359. cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
  1360. cortex_m3_init_arch_info(target, cortex_m3, target->tap);
  1361. return ERROR_OK;
  1362. }
  1363. /*
  1364. * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
  1365. * as at least ARM-1156T2. The interesting thing about Cortex-M is
  1366. * that *only* Thumb2 disassembly matters. There are also some small
  1367. * additions to Thumb2 that are specific to ARMv7-M.
  1368. */
  1369. static int
  1370. handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx,
  1371. char *cmd, char **args, int argc)
  1372. {
  1373. int retval = ERROR_OK;
  1374. target_t *target = get_current_target(cmd_ctx);
  1375. uint32_t address;
  1376. unsigned long count = 1;
  1377. arm_instruction_t cur_instruction;
  1378. errno = 0;
  1379. switch (argc) {
  1380. case 2:
  1381. count = strtoul(args[1], NULL, 0);
  1382. if (errno)
  1383. return ERROR_FAIL;
  1384. /* FALL THROUGH */
  1385. case 1:
  1386. address = strtoul(args[0], NULL, 0);
  1387. if (errno)
  1388. return ERROR_FAIL;
  1389. break;
  1390. default:
  1391. command_print(cmd_ctx,
  1392. "usage: cortex_m3 disassemble <address> [<count>]");
  1393. return ERROR_OK;
  1394. }
  1395. while (count--) {
  1396. retval = thumb2_opcode(target, address, &cur_instruction);
  1397. if (retval != ERROR_OK)
  1398. return retval;
  1399. command_print(cmd_ctx, "%s", cur_instruction.text);
  1400. address += cur_instruction.instruction_size;
  1401. }
  1402. return ERROR_OK;
  1403. }
  1404. static const struct {
  1405. char name[10];
  1406. unsigned mask;
  1407. } vec_ids[] = {
  1408. { "hard_err", VC_HARDERR, },
  1409. { "int_err", VC_INTERR, },
  1410. { "bus_err", VC_BUSERR, },
  1411. { "state_err", VC_STATERR, },
  1412. { "chk_err", VC_CHKERR, },
  1413. { "nocp_err", VC_NOCPERR, },
  1414. { "mm_err", VC_MMERR, },
  1415. { "reset", VC_CORERESET, },
  1416. };
  1417. static int
  1418. handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx,
  1419. char *cmd, char **argv, int argc)
  1420. {
  1421. target_t *target = get_current_target(cmd_ctx);
  1422. armv7m_common_t *armv7m = target->arch_info;
  1423. swjdp_common_t *swjdp = &armv7m->swjdp_info;
  1424. uint32_t demcr = 0;
  1425. int i;
  1426. mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
  1427. if (argc > 0) {
  1428. unsigned catch = 0;
  1429. if (argc == 1) {
  1430. if (strcmp(argv[0], "all") == 0) {
  1431. catch = VC_HARDERR | VC_INTERR | VC_BUSERR
  1432. | VC_STATERR | VC_CHKERR | VC_NOCPERR
  1433. | VC_MMERR | VC_CORERESET;
  1434. goto write;
  1435. } else if (strcmp(argv[0], "none") == 0) {
  1436. goto write;
  1437. }
  1438. }
  1439. while (argc-- > 0) {
  1440. for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
  1441. if (strcmp(argv[argc], vec_ids[i].name) != 0)
  1442. continue;
  1443. catch |= vec_ids[i].mask;
  1444. break;
  1445. }
  1446. if (i == ARRAY_SIZE(vec_ids)) {
  1447. LOG_ERROR("No CM3 vector '%s'", argv[argc]);
  1448. return ERROR_INVALID_ARGUMENTS;
  1449. }
  1450. }
  1451. write:
  1452. demcr &= ~0xffff;
  1453. demcr |= catch;
  1454. /* write, but don't assume it stuck */
  1455. mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
  1456. mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
  1457. }
  1458. for (i = 0; i < ARRAY_SIZE(vec_ids); i++)
  1459. command_print(cmd_ctx, "%9s: %s", vec_ids[i].name,
  1460. (demcr & vec_ids[i].mask) ? "catch" : "ignore");
  1461. return ERROR_OK;
  1462. }
  1463. static int
  1464. handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx,
  1465. ch