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cortex_m3.h 5.3 KiB

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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifndef CORTEX_M3_H
  27. #define CORTEX_M3_H
  28. #include "register.h"
  29. #include "target.h"
  30. #include "armv7m.h"
  31. #define CORTEX_M3_COMMON_MAGIC 0x1A451A45
  32. #define SYSTEM_CONTROL_BASE 0x400FE000
  33. #define CPUID 0xE000ED00
  34. /* Debug Control Block */
  35. #define DCB_DHCSR 0xE000EDF0
  36. #define DCB_DCRSR 0xE000EDF4
  37. #define DCB_DCRDR 0xE000EDF8
  38. #define DCB_DEMCR 0xE000EDFC
  39. #define DCRSR_WnR (1 << 16)
  40. #define DWT_CTRL 0xE0001000
  41. #define DWT_COMP0 0xE0001020
  42. #define DWT_MASK0 0xE0001024
  43. #define DWT_FUNCTION0 0xE0001028
  44. #define FP_CTRL 0xE0002000
  45. #define FP_REMAP 0xE0002004
  46. #define FP_COMP0 0xE0002008
  47. #define FP_COMP1 0xE000200C
  48. #define FP_COMP2 0xE0002010
  49. #define FP_COMP3 0xE0002014
  50. #define FP_COMP4 0xE0002018
  51. #define FP_COMP5 0xE000201C
  52. #define FP_COMP6 0xE0002020
  53. #define FP_COMP7 0xE0002024
  54. #define DWT_CTRL 0xE0001000
  55. /* DCB_DHCSR bit and field definitions */
  56. #define DBGKEY (0xA05F << 16)
  57. #define C_DEBUGEN (1 << 0)
  58. #define C_HALT (1 << 1)
  59. #define C_STEP (1 << 2)
  60. #define C_MASKINTS (1 << 3)
  61. #define S_REGRDY (1 << 16)
  62. #define S_HALT (1 << 17)
  63. #define S_SLEEP (1 << 18)
  64. #define S_LOCKUP (1 << 19)
  65. #define S_RETIRE_ST (1 << 24)
  66. #define S_RESET_ST (1 << 25)
  67. /* DCB_DEMCR bit and field definitions */
  68. #define TRCENA (1 << 24)
  69. #define VC_HARDERR (1 << 10)
  70. #define VC_INTERR (1 << 9)
  71. #define VC_BUSERR (1 << 8)
  72. #define VC_STATERR (1 << 7)
  73. #define VC_CHKERR (1 << 6)
  74. #define VC_NOCPERR (1 << 5)
  75. #define VC_MMERR (1 << 4)
  76. #define VC_CORERESET (1 << 0)
  77. #define NVIC_ICTR 0xE000E004
  78. #define NVIC_ISE0 0xE000E100
  79. #define NVIC_ICSR 0xE000ED04
  80. #define NVIC_AIRCR 0xE000ED0C
  81. #define NVIC_SHCSR 0xE000ED24
  82. #define NVIC_CFSR 0xE000ED28
  83. #define NVIC_MMFSRb 0xE000ED28
  84. #define NVIC_BFSRb 0xE000ED29
  85. #define NVIC_USFSRh 0xE000ED2A
  86. #define NVIC_HFSR 0xE000ED2C
  87. #define NVIC_DFSR 0xE000ED30
  88. #define NVIC_MMFAR 0xE000ED34
  89. #define NVIC_BFAR 0xE000ED38
  90. /* NVIC_AIRCR bits */
  91. #define AIRCR_VECTKEY (0x5FA << 16)
  92. #define AIRCR_SYSRESETREQ (1 << 2)
  93. #define AIRCR_VECTCLRACTIVE (1 << 1)
  94. #define AIRCR_VECTRESET (1 << 0)
  95. /* NVIC_SHCSR bits */
  96. #define SHCSR_BUSFAULTENA (1 << 17)
  97. /* NVIC_DFSR bits */
  98. #define DFSR_HALTED 1
  99. #define DFSR_BKPT 2
  100. #define DFSR_DWTTRAP 4
  101. #define DFSR_VCATCH 8
  102. #define FPCR_CODE 0
  103. #define FPCR_LITERAL 1
  104. #define FPCR_REPLACE_REMAP (0 << 30)
  105. #define FPCR_REPLACE_BKPT_LOW (1 << 30)
  106. #define FPCR_REPLACE_BKPT_HIGH (2 << 30)
  107. #define FPCR_REPLACE_BKPT_BOTH (3 << 30)
  108. typedef struct cortex_m3_fp_comparator_s
  109. {
  110. int used;
  111. int type;
  112. uint32_t fpcr_value;
  113. uint32_t fpcr_address;
  114. } cortex_m3_fp_comparator_t;
  115. typedef struct cortex_m3_dwt_comparator_s
  116. {
  117. int used;
  118. uint32_t comp;
  119. uint32_t mask;
  120. uint32_t function;
  121. uint32_t dwt_comparator_address;
  122. } cortex_m3_dwt_comparator_t;
  123. typedef struct cortex_m3_common_s
  124. {
  125. int common_magic;
  126. arm_jtag_t jtag_info;
  127. /* Context information */
  128. uint32_t dcb_dhcsr;
  129. uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
  130. uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
  131. /* Flash Patch and Breakpoint (FPB) */
  132. int fp_num_lit;
  133. int fp_num_code;
  134. int fp_code_available;
  135. int fpb_enabled;
  136. int auto_bp_type;
  137. cortex_m3_fp_comparator_t *fp_comparator_list;
  138. /* Data Watchpoint and Trace (DWT) */
  139. int dwt_num_comp;
  140. int dwt_comp_available;
  141. cortex_m3_dwt_comparator_t *dwt_comparator_list;
  142. /* Interrupts */
  143. int intlinesnum;
  144. uint32_t *intsetenable;
  145. armv7m_common_t armv7m;
  146. void *arch_info;
  147. } cortex_m3_common_t;
  148. #endif /* CORTEX_M3_H */