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dm355evm.cfg 5.1 KiB

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  1. # DM355 EVM board
  2. # http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
  3. # http://c6000.spectrumdigital.com/evmdm355/
  4. source [find target/ti_dm355.cfg]
  5. reset_config trst_and_srst separate
  6. # NOTE: disable or replace this call to dm355evm_init if you're
  7. # debugging new UBL code from SRAM.
  8. $_TARGETNAME configure -event reset-init { dm355evm_init }
  9. #
  10. # This post-reset init is called when the MMU isn't active, all IRQs
  11. # are disabled, etc. It should do most of what a UBL does, except for
  12. # loading code (like U-Boot) into DRAM and running it.
  13. #
  14. proc dm355evm_init {} {
  15. global dm355
  16. echo "Initialize DM355 EVM board"
  17. # CLKIN = 24 MHz ... can't talk quickly to ARM yet
  18. jtag_rclk 1500
  19. ########################
  20. # PLL1 = 432 MHz (/8, x144)
  21. # ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
  22. # ...SYSCLK2 = 108 MHz (/4) ... Peripherals
  23. # ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
  24. # ...SYSCLK4 = 108 MHz (/4) ... VPSS
  25. # pll1.{prediv,div1,div2} are fixed
  26. # pll1.postdiv set in MISC (for *this* speed grade)
  27. set addr [dict get $dm355 pllc1]
  28. set pll_divs [dict create]
  29. dict set pll_divs div3 16
  30. dict set pll_divs div4 4
  31. pll_v02_setup $addr 144 $pll_divs
  32. # ARM is now running at 216 MHz, so JTAG can go faster
  33. jtag_rclk 20000
  34. ########################
  35. # PLL2 = 342 MHz (/8, x114)
  36. # ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
  37. # pll2.{postdiv,div1} are fixed
  38. set addr [dict get $dm355 pllc2]
  39. set pll_divs [dict create]
  40. dict set pll_divs div1 1
  41. dict set pll_divs prediv 8
  42. pll_v02_setup $addr 114 $pll_divs
  43. ########################
  44. # PINMUX
  45. # All Video Inputs
  46. davinci_pinmux $dm355 0 0x00007f55
  47. # All Video Outputs
  48. davinci_pinmux $dm355 1 0x00145555
  49. # EMIFA (NOTE: more could be set up for use as GPIOs)
  50. davinci_pinmux $dm355 2 0x00000c08
  51. # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
  52. davinci_pinmux $dm355 3 0x1bff55ff
  53. # MMC/SD0 instead of MS; SPI0
  54. davinci_pinmux $dm355 4 0x00000000
  55. ########################
  56. # PSC setup (minimal)
  57. # DDR EMIF/13, AEMIF/14, UART0/19
  58. psc_enable 13
  59. psc_enable 14
  60. psc_enable 19
  61. psc_go
  62. ########################
  63. # DDR2 EMIF
  64. # VTPIOCR impedance calibration
  65. set addr [dict get $dm355 sysbase]
  66. set addr [expr $addr + 0x70]
  67. # clear CLR, LOCK, PWRDN; wait a clock; set CLR
  68. mmw $addr 0 0x20c0
  69. mmw $addr 0x2000 0
  70. # wait for READY
  71. while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }
  72. # set IO_READY; then LOCK and PWRSAVE; then PWRDN
  73. mmw $addr 0x4000 0
  74. mmw $addr 0x0180 0
  75. mmw $addr 0x0040 0
  76. # NOTE: this DDR2 initialization sequence borrows from
  77. # both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
  78. # reset (then re-enable) DDR controller
  79. psc_reset 13
  80. psc_go
  81. psc_enable 13
  82. psc_go
  83. # now set it up for Micron MT47H64M16HR-37E @ 171 MHz
  84. set addr [dict get $dm355 ddr_emif]
  85. # DDRPHYCR1
  86. mww [expr $addr + 0xe4] 0x50006404
  87. # PBBPR -- burst priority
  88. mww [expr $addr + 0x20] 0xfe
  89. # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
  90. mmw [expr $addr + 0x08] 0x00800000 0
  91. mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
  92. # SDTIMR0, SDTIMR1
  93. mww [expr $addr + 0x10] 0x2a923249
  94. mww [expr $addr + 0x14] 0x4c17c763
  95. # SDCR -- relock SDTIM*
  96. mmw [expr $addr + 0x08] 0 0x00008000
  97. # SDRCR -- refresh rate (171 MHz * 7.8usec)
  98. mww [expr $addr + 0x0c] 1336
  99. ########################
  100. # ASYNC EMIF
  101. set addr [dict get $dm355 a_emif]
  102. # slow/pessimistic timings
  103. set nand_timings 0x40400204
  104. # fast (25% faster page reads)
  105. #set nand_timings 0x0400008c
  106. # AWCCR
  107. mww [expr $addr + 0x04] 0xff
  108. # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
  109. mww [expr $addr + 0x10] $nand_timings
  110. # CS1 == dm9000 Ethernet
  111. mww [expr $addr + 0x14] 0x00a00505
  112. # NANDFCR -- only CS0 has NAND
  113. mww [expr $addr + 0x60] 0x01
  114. # default: both chipselects to the NAND socket are used
  115. nand probe 0
  116. nand probe 1
  117. ########################
  118. # UART0
  119. set addr [dict get $dm355 uart0]
  120. # PWREMU_MGNT -- rx + tx in reset
  121. mww [expr $addr + 0x30] 0
  122. # DLL, DLH -- 115200 baud
  123. mwb [expr $addr + 0x20] 0x0d
  124. mwb [expr $addr + 0x24] 0x00
  125. # FCR - clear and disable FIFOs
  126. mwb [expr $addr + 0x08] 0x07
  127. mwb [expr $addr + 0x08] 0x00
  128. # IER - disable IRQs
  129. mwb [expr $addr + 0x04] 0x00
  130. # LCR - 8-N-1
  131. mwb [expr $addr + 0x0c] 0x03
  132. # MCR - no flow control or loopback
  133. mwb [expr $addr + 0x10] 0x00
  134. # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
  135. mww [expr $addr + 0x30] 0xe001
  136. ########################
  137. # turn on icache - set I bit in cp15 register c1
  138. arm mcr 15 0 0 1 0 0x00051078
  139. }
  140. # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
  141. #
  142. # NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND
  143. # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
  144. # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
  145. # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
  146. set _FLASHNAME $_CHIPNAME.boot
  147. nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
  148. set _FLASHNAME $_CHIPNAME.flash
  149. nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
  150. # FIXME
  151. # - support writing UBL with its header (new layout only with new ROMs)
  152. # - support writing ABL/U-Boot with its header (new layout)