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spear3xx_ddr.tcl 4.6 KiB

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  1. # Init scripts to configure DDR controller of SPEAr3xx
  2. # http://www.st.com/spear
  3. # Original values taken from XLoader source code
  4. #
  5. # Date: 2010-09-23
  6. # Author: Antonio Borneo <borneo.antonio@gmail.com>
  7. proc sp3xx_ddr_init {ddr_type} {
  8. if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
  9. ddr_spr3xx_mt47h64m16_3_333_cl5_async
  10. set ddr_size 0x08000000
  11. ## add here new DDR chip definition. Prototype:
  12. #} elseif { $ddr_type == "?????" } {
  13. # ?????
  14. # set ddr_size 0x?????
  15. } else {
  16. error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
  17. }
  18. # Check for single/double memory chip
  19. # DDR starts at address 0x00000000
  20. mww $ddr_size 0x87654321
  21. mww 0x00000000 0x12345678
  22. if {[expr [mrw 0x00000000] == 0x12345678 && [mrw $ddr_size] == 0x87654321]} {
  23. echo [format \
  24. "Double chip DDR memory. Total memory size 0x%08x byte" \
  25. [expr 2 * $ddr_size]]
  26. } else {
  27. echo [format \
  28. "Single chip DDR memory. Memory size 0x%08x byte" \
  29. $ddr_size]
  30. }
  31. }
  32. # from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
  33. proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {} {
  34. # DDR_PAD_REG
  35. mww 0xfca800f0 0x00003aa5
  36. # Use "1:2 sync" only when DDR clock source is PLL1 and
  37. # HCLK is half of PLL1
  38. mww 0xfc600000 0x00000001 # MEMCTL_AHB_SET_00 # This is async
  39. mww 0xfc600004 0x00000000 # MEMCTL_AHB_SET_01
  40. # mww 0xfc600000 0x02020201 # MEMCTL_AHB_SET_00 # This is 1:2 sync
  41. # mww 0xfc600004 0x02020202 # MEMCTL_AHB_SET_01
  42. mww 0xfc600008 0x01000000 # MEMCTL_RFSH_SET_00
  43. mww 0xfc60000c 0x00000101 # MEMCTL_DLL_SET_00
  44. mww 0xfc600010 0x00000101 # MEMCTL_GP_00
  45. mww 0xfc600014 0x01000000 # MEMCTL_GP_01
  46. mww 0xfc600018 0x00010001 # MEMCTL_GP_02
  47. mww 0xfc60001c 0x00000100 # MEMCTL_GP_03
  48. mww 0xfc600020 0x00010001 # MEMCTL_GP_04
  49. mww 0xfc600024 0x01020203 # MEMCTL_GP_05
  50. mww 0xfc600028 0x01000102 # MEMCTL_GP_06
  51. mww 0xfc60002c 0x02000202 # MEMCTL_AHB_SET_02
  52. mww 0xfc600030 0x04040105 # MEMCTL_AHB_SET_03
  53. mww 0xfc600034 0x03030302 # MEMCTL_AHB_SET_04
  54. mww 0xfc600038 0x02040101 # MEMCTL_AHB_SET_05
  55. mww 0xfc60003c 0x00000002 # MEMCTL_AHB_SET_06
  56. mww 0xfc600044 0x03000405 # MEMCTL_DQS_SET_0
  57. mww 0xfc600048 0x03040002 # MEMCTL_TIME_SET_01
  58. mww 0xfc60004c 0x04000305 # MEMCTL_TIME_SET_02
  59. mww 0xfc600050 0x0505053f # MEMCTL_AHB_RELPR_00
  60. mww 0xfc600054 0x05050505 # MEMCTL_AHB_RELPR_01
  61. mww 0xfc600058 0x04040405 # MEMCTL_AHB_RELPR_02
  62. mww 0xfc60005c 0x04040404 # MEMCTL_AHB_RELPR_03
  63. mww 0xfc600060 0x03030304 # MEMCTL_AHB_RELPR_04
  64. mww 0xfc600064 0x03030303 # MEMCTL_AHB_RELPR_05
  65. mww 0xfc600068 0x02020203 # MEMCTL_AHB_RELPR_06
  66. mww 0xfc60006c 0x02020202 # MEMCTL_AHB_RELPR_07
  67. mww 0xfc600070 0x01010102 # MEMCTL_AHB_RELPR_08
  68. mww 0xfc600074 0x01010101 # MEMCTL_AHB_RELPR_09
  69. mww 0xfc600078 0x00000001 # MEMCTL_AHB_RELPR_10
  70. mww 0xfc600088 0x0a0c0a00 # MEMCTL_DQS_SET_1
  71. mww 0xfc60008c 0x0000023f # MEMCTL_GP_07
  72. mww 0xfc600090 0x00050a00 # MEMCTL_GP_08
  73. mww 0xfc600094 0x11000000 # MEMCTL_GP_09
  74. mww 0xfc600098 0x00001302 # MEMCTL_GP_10
  75. mww 0xfc60009c 0x00001c1c # MEMCTL_DLL_SET_01
  76. mww 0xfc6000a0 0x7c000000 # MEMCTL_DQS_OUT_SHIFT
  77. mww 0xfc6000a4 0x005c0000 # MEMCTL_WR_DQS_SHIFT
  78. mww 0xfc6000a8 0x2b050e00 # MEMCTL_TIME_SET_03
  79. mww 0xfc6000ac 0x00640064 # MEMCTL_AHB_PRRLX_00
  80. mww 0xfc6000b0 0x00640064 # MEMCTL_AHB_PRRLX_01
  81. mww 0xfc6000b4 0x00000064 # MEMCTL_AHB_PRRLX_02
  82. mww 0xfc6000b8 0x00000000 # MEMCTL_OUTRANGE_LGTH
  83. mww 0xfc6000bc 0x00200020 # MEMCTL_AHB_RW_SET_00
  84. mww 0xfc6000c0 0x00200020 # MEMCTL_AHB_RW_SET_01
  85. mww 0xfc6000c4 0x00200020 # MEMCTL_AHB_RW_SET_02
  86. mww 0xfc6000c8 0x00200020 # MEMCTL_AHB_RW_SET_03
  87. mww 0xfc6000cc 0x00200020 # MEMCTL_AHB_RW_SET_04
  88. mww 0xfc6000d8 0x00000a24 # MEMCTL_TREF
  89. mww 0xfc6000dc 0x00000000 # MEMCTL_EMRS3_DATA
  90. mww 0xfc6000e0 0x5b1c00c8 # MEMCTL_TIME_SET_04
  91. mww 0xfc6000e4 0x00c8002e # MEMCTL_TIME_SET_05
  92. mww 0xfc6000e8 0x00000000 # MEMCTL_VERSION
  93. mww 0xfc6000ec 0x0001046b # MEMCTL_TINIT
  94. mww 0xfc6000f0 0x00000000 # MEMCTL_OUTRANGE_ADDR_01
  95. mww 0xfc6000f4 0x00000000 # MEMCTL_OUTRANGE_ADDR_02
  96. mww 0xfc600104 0x001c0000 # MEMCTL_DLL_DQS_DELAY_BYPASS_0
  97. mww 0xfc600108 0x0019001c # MEMCTL_DLL_SET_02
  98. mww 0xfc60010c 0x00100000 # MEMCTL_DLL_SET_03
  99. mww 0xfc600110 0x001e007a # MEMCTL_DQS_SET_2
  100. mww 0xfc600188 0x00000000 # MEMCTL_USER_DEF_REG_0
  101. mww 0xfc60018c 0x00000000 # MEMCTL_USER_DEF_REG_1
  102. mww 0xfc600190 0x01010001 # MEMCTL_GP_11
  103. mww 0xfc600194 0x01000000 # MEMCTL_GP_12
  104. mww 0xfc600198 0x00000001 # MEMCTL_GP_13
  105. mww 0xfc60019c 0x00400000 # MEMCTL_GP_14
  106. mww 0xfc6001a0 0x00000000 # MEMCTL_EMRS2_DATA_X
  107. mww 0xfc6001a4 0x00000000 # MEMCTL_LWPWR_CNT
  108. mww 0xfc6001a8 0x00000000 # MEMCTL_LWPWR_REG
  109. mww 0xfc6001ac 0x00860000 # MEMCTL_GP_15
  110. mww 0xfc6001b0 0x00000002 # MEMCTL_TPDEX
  111. # MPMC START
  112. mww 0xfc60001c 0x01000100
  113. }