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@@ -1,5 +1,5 @@ |
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/*************************************************************************** |
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* Copyright (C) 2008 by Marvell Semiconductors, Inc. * |
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* Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. * |
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* Written by Nicolas Pitre <nico@marvell.com> * |
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* * |
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* Copyright (C) 2008 by Hongtao Zheng * |
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@@ -22,10 +22,10 @@ |
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***************************************************************************/ |
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/* |
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* Marvell Feroceon support, including Orion and Kirkwood SOCs. |
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* Marvell Feroceon/Dragonite support. |
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* |
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* The Feroceon core mimics the ARM926 ICE interface with the following |
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* differences: |
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* The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others, |
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* mimics the ARM926 ICE interface with the following differences: |
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* |
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* - the MOE (method of entry) reporting is not implemented |
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* |
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@@ -43,6 +43,9 @@ |
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* |
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* - the DCC channel is half duplex (only one FIFO for both directions) with |
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* seemingly no proper flow control. |
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* |
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* The Dragonite core is the non-mmu version based on the ARM966 model, and |
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* it shares the above issues as well. |
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*/ |
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#ifdef HAVE_CONFIG_H |
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@@ -50,11 +53,13 @@ |
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#endif |
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#include "arm926ejs.h" |
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#include "arm966e.h" |
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#include "target_type.h" |
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int feroceon_examine(struct target_s *target); |
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int feroceon_target_create(struct target_s *target, Jim_Interp *interp); |
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int dragonite_target_create(struct target_s *target, Jim_Interp *interp); |
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int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); |
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int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); |
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int feroceon_quit(void); |
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@@ -111,6 +116,44 @@ target_type_t feroceon_target = |
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.quit = feroceon_quit |
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}; |
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target_type_t dragonite_target = |
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{ |
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.name = "dragonite", |
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.poll = arm7_9_poll, |
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.arch_state = armv4_5_arch_state, |
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.target_request_data = arm7_9_target_request_data, |
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.halt = arm7_9_halt, |
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.resume = arm7_9_resume, |
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.step = arm7_9_step, |
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.assert_reset = feroceon_assert_reset, |
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.deassert_reset = arm7_9_deassert_reset, |
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.soft_reset_halt = arm7_9_soft_reset_halt, |
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.get_gdb_reg_list = armv4_5_get_gdb_reg_list, |
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.read_memory = arm7_9_read_memory, |
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.write_memory = arm7_9_write_memory, |
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.bulk_write_memory = feroceon_bulk_write_memory, |
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.checksum_memory = arm7_9_checksum_memory, |
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.blank_check_memory = arm7_9_blank_check_memory, |
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.run_algorithm = armv4_5_run_algorithm, |
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.add_breakpoint = arm7_9_add_breakpoint, |
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.remove_breakpoint = arm7_9_remove_breakpoint, |
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.add_watchpoint = arm7_9_add_watchpoint, |
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.remove_watchpoint = arm7_9_remove_watchpoint, |
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.register_commands = arm966e_register_commands, |
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.target_create = dragonite_target_create, |
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.init_target = feroceon_init_target, |
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.examine = feroceon_examine, |
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.quit = feroceon_quit |
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}; |
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int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) |
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{ |
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@@ -632,16 +675,10 @@ int feroceon_quit(void) |
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return ERROR_OK; |
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} |
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int feroceon_target_create(struct target_s *target, Jim_Interp *interp) |
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void feroceon_common_setup(struct target_s *target) |
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{ |
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armv4_5_common_t *armv4_5; |
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arm7_9_common_t *arm7_9; |
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arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); |
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arm926ejs_init_arch_info(target, arm926ejs, target->tap); |
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armv4_5 = target->arch_info; |
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arm7_9 = armv4_5->arch_info; |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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/* override some insn sequence functions */ |
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arm7_9->change_to_arm = feroceon_change_to_arm; |
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@@ -661,10 +698,6 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) |
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/* MOE is not implemented */ |
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arm7_9->examine_debug_reason = feroceon_examine_debug_reason; |
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/* the standard ARM926 methods don't always work (don't ask...) */ |
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arm926ejs->read_cp15 = feroceon_read_cp15; |
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arm926ejs->write_cp15 = feroceon_write_cp15; |
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/* Note: asserting DBGRQ might not win over the undef exception. |
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If that happens then just use "arm7_9 dbgrq disable". */ |
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arm7_9->use_dbgrq = 1; |
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@@ -673,6 +706,28 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) |
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/* only one working comparator */ |
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arm7_9->wp_available_max = 1; |
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arm7_9->wp1_used_default = -1; |
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} |
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int feroceon_target_create(struct target_s *target, Jim_Interp *interp) |
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{ |
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arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); |
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arm926ejs_init_arch_info(target, arm926ejs, target->tap); |
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feroceon_common_setup(target); |
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/* the standard ARM926 methods don't always work (don't ask...) */ |
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arm926ejs->read_cp15 = feroceon_read_cp15; |
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arm926ejs->write_cp15 = feroceon_write_cp15; |
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return ERROR_OK; |
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} |
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int dragonite_target_create(struct target_s *target, Jim_Interp *interp) |
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{ |
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arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t)); |
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arm966e_init_arch_info(target, arm966e, target->tap); |
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feroceon_common_setup(target); |
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return ERROR_OK; |
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} |
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