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Merge commit 'origin/master'

Øyvind Harboe 14 years ago
9 changed files with 438 additions and 322 deletions
  1. +126
  2. +6
  3. +15
  4. +2
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  6. +4
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  8. +243
  9. +12

+ 126
- 28
doc/openocd.texi View File

@@ -66,7 +66,6 @@ Free Documentation License''.
* Running:: Running OpenOCD
* OpenOCD Project Setup:: OpenOCD Project Setup
* Config File Guidelines:: Config File Guidelines
* Translating Configuration Files:: Translating Configuration Files
* Daemon Configuration:: Daemon Configuration
* Interface - Dongle Configuration:: Interface - Dongle Configuration
* Reset Configuration:: Reset Configuration
@@ -1186,7 +1185,9 @@ handlers too, if just for developer convenience.
Because this is so very board-specific, and chip-specific, no examples
are included here.
Instead, look at the board config files distributed with OpenOCD.
If you have a boot loader, its source code may also be useful.
If you have a boot loader, its source code will help; so will
configuration files for other JTAG tools
(@pxref{Translating Configuration Files}).
@end quotation

Some of this code could probably be shared between different boards.
@@ -1464,17 +1465,18 @@ Examples:
@item pxa270 - again - CS0 flash - it goes in the board file.
@end itemize

@node Translating Configuration Files
@chapter Translating Configuration Files
@anchor{Translating Configuration Files}
@section Translating Configuration Files
@cindex translation
If you have a configuration file for another hardware debugger(Abatron,
BDI2000, BDI3000, Lauterbach, Segger, MacRaigor, etc.), translating
If you have a configuration file for another hardware debugger
or toolset (Abatron, BDI2000, BDI3000, CCS,
Lauterbach, Segger, Macraigor, etc.), translating
it into OpenOCD syntax is often quite straightforward. The most tricky
part of creating a configuration script is oftentimes the reset init
sequence where e.g. PLLs, DRAM and the like is set up.

One trick that you can use when translating is to write small
Tcl proc's to translate the syntax into OpenOCD syntax. This
Tcl procedures to translate the syntax into OpenOCD syntax. This
can avoid manual translation errors and make it easier to
convert other scripts later on.

@@ -1482,23 +1484,22 @@ Example of transforming quirky arguments to a simple search and
replace job:

# rewrite commands of the form below to arm11 mcr...
# Lauterbach syntax(?)
# Data.Set c15:0x042f %long 0x40000015
# Data.Set c15:0x042f %long 0x40000015
# OpenOCD syntax when using procedure below.
# setc15 0x01 0x00050078
# setc15 0x01 0x00050078

proc setc15 @{regs value@} @{

echo [format "set p15 0x%04x, 0x%08x" $regs $value]
echo [format "set p15 0x%04x, 0x%08x" $regs $value]

arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
[expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
[expr ($regs>>8)&0x7] $value
@end example

@@ -1563,6 +1564,17 @@ read/write memory on your target, @command{init} must occur before
the memory read/write commands. This includes @command{nand probe}.
@end deffn

@deffn {Overridable Procedure} jtag_init
This is invoked at server startup to verify that it can talk
to the scan chain (list of TAPs) which has been configured.

The default implementation first tries @command{jtag arp_init},
which uses only a lightweight JTAG reset before examining the
scan chain.
If that fails, it tries again, using a harder reset
from the overridable procedure @command{init_reset}.
@end deffn

@anchor{TCP/IP Ports}
@section TCP/IP Ports
@cindex TCP port
@@ -2192,8 +2204,9 @@ issues (not limited to errata).
For example, certain JTAG commands might need to be issued while
the system as a whole is in a reset state (SRST active)
but the JTAG scan chain is usable (TRST inactive).
(@xref{JTAG Commands}, where the @command{jtag_reset}
command is presented.)
Many systems treat combined assertion of SRST and TRST as a
trigger for a harder reset than SRST alone.
Such custom reset handling is discussed later in this chapter.
@end itemize

There can also be other issues.
@@ -2260,7 +2273,7 @@ Possible values are @option{none} (the default), @option{trst_only},

@quotation Tip
If your board provides SRST and/or TRST through the JTAG connector,
you must declare that or else those signals will not be used.
you must declare that so those signals can be used.
@end quotation

@@ -2309,6 +2322,82 @@ powerup and pressing a reset button.
@end itemize
@end deffn

@section Custom Reset Handling
@cindex events

OpenOCD has several ways to help support the various reset
mechanisms provided by chip and board vendors.
The commands shown in the previous section give standard parameters.
There are also @emph{event handlers} associated with TAPs or Targets.
Those handlers are Tcl procedures you can provide, which are invoked
at particular points in the reset sequence.

After configuring those mechanisms, you might still
find your board doesn't start up or reset correctly.
For example, maybe it needs a slightly different sequence
of SRST and/or TRST manipulations, because of quirks that
the @command{reset_config} mechanism doesn't address;
or asserting both might trigger a stronger reset, which
needs special attention.

Experiment with lower level operations, such as @command{jtag_reset}
and the @command{jtag arp_*} operations shown here,
to find a sequence of operations that works.
@xref{JTAG Commands}.
When you find a working sequence, it can be used to override
@command{jtag_init}, which fires during OpenOCD startup
(@pxref{Configuration Stage});
or @command{init_reset}, which fires during reset processing.

You might also want to provide some project-specific reset
schemes. For example, on a multi-target board the standard
@command{reset} command would reset all targets, but you
may need the ability to reset only one target at time and
thus want to avoid using the board-wide SRST signal.

@deffn {Overridable Procedure} init_reset mode
This is invoked near the beginning of the @command{reset} command,
usually to provide as much of a cold (power-up) reset as practical.
By default it is also invoked from @command{jtag_init} if
the scan chain does not respond to pure JTAG operations.
The @var{mode} parameter is the parameter given to the
low level reset command (@option{halt},
@option{init}, or @option{run}), @option{setup},
or potentially some other value.

The default implementation just invokes @command{jtag arp_init-reset}.
Replacements will normally build on low level JTAG
operations such as @command{jtag_reset}.
Operations here must not address individual TAPs
(or their associated targets)
until the JTAG scan chain has first been verified to work.

Implementations must have verified the JTAG scan chain before
they return.
This is done by calling @command{jtag arp_init}
(or @command{jtag arp_init-reset}).
@end deffn

@deffn Command {jtag arp_init}
This validates the scan chain using just the four
standard JTAG signals (TMS, TCK, TDI, TDO).
It starts by issuing a JTAG-only reset.
Then it performs checks to verify that the scan chain configuration
matches the TAPs it can observe.
Those checks include checking IDCODE values for each active TAP,
and verifying the length of their instruction registers using
TAP @code{-ircapture} and @code{-irmask} values.
If these tests all pass, TAP @code{setup} events are
issued to all TAPs with handlers for that event.
@end deffn

@deffn Command {jtag arp_init-reset}
This uses TRST and SRST to try resetting
everything on the JTAG scan chain
(and anything else connected to SRST).
It then invokes the logic of @command{jtag arp_init}.
@end deffn

@node TAP Declaration
@chapter TAP Declaration
@@ -2540,9 +2629,6 @@ there seems to be no problems with JTAG scan chain operations.

@section Other TAP commands

@c @deffn Command {jtag arp_init-reset}
@c ... more or less "toggle TRST ... and SRST too, what the heck"

@deffn Command {jtag cget} @option{-event} name
@deffnx Command {jtag configure} @option{-event} name string
At this writing this TAP attribute
@@ -3218,7 +3304,7 @@ The following target events are defined:
@end ignore
@item @b{reset-assert-pre}
@* Issued as part of @command{reset} processing
after SRST and/or TRST were activated and deactivated,
after @command{reset_init} was triggered
but before SRST alone is re-asserted on the tap.
@item @b{reset-assert-post}
@* Issued as part of @command{reset} processing
@@ -3248,10 +3334,11 @@ multiplexing, and so on.
the target clocks are fully set up.)
@item @b{reset-start}
@* Issued as part of @command{reset} processing
before either SRST or TRST are activated.
before @command{reset_init} is called.

This is the most robust place to switch to a low JTAG clock rate, if
SRST disables PLLs needed to use a fast clock.
This is the most robust place to use @command{jtag_rclk}
or @command{jtag_khz} to switch to a low JTAG clock rate,
when reset disables PLLs needed to use a fast clock.
@item @b{reset-wait-pos}
@* Currently not used
@@ -5983,6 +6070,17 @@ The @command{reset_config} command should already have been used
to configure how the board and JTAG adapter treat these two
signals, and to say if either signal is even present.
@xref{Reset Configuration}.

Note that TRST is specially handled.
It actually signifies JTAG's @sc{reset} state.
So if the board doesn't support the optional TRST signal,
or it doesn't support it along with the specified SRST value,
JTAG reset is triggered with TMS and TCK signals
instead of the TRST signal.
And no matter how that JTAG reset is triggered, once
the scan chain enters @sc{reset} with TRST inactive,
TAP @code{post-reset} events are delivered to all TAPs
with handlers for that event.
@end deffn

@deffn Command {runtest} @var{num_cycles}
@@ -6015,7 +6113,7 @@ The @var{tap_state} names used by OpenOCD in the @command{drscan},
and @command{irscan} commands are:

@itemize @bullet
@item @b{RESET} ... should act as if TRST were active
@item @b{RESET} ... acts as if TRST were pulsed
@item @b{RUN/IDLE} ... don't assume this always means IDLE
@item @b{DRSELECT}
@item @b{DRCAPTURE}
@@ -6046,7 +6144,7 @@ may not be as expected.
@item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
choices after @command{drscan} or @command{irscan} commands,
since they are free of JTAG side effects.
However, @sc{run/idle} may have side effects that appear at other
@item @sc{run/idle} may have side effects that appear at non-JTAG
levels, such as advancing the ARM9E-S instruction pipeline.
Consult the documentation for the TAP(s) you are working with.
@end itemize

+ 6
- 5
src/flash/flash.c View File

@@ -569,8 +569,8 @@ static int flash_check_sector_parameters(struct command_context_s *cmd_ctx,

if (!(last <= (num_sectors - 1))) {
command_print(cmd_ctx, "ERROR: "
"last sector must be <= %d", num_sectors - 1);
command_print(cmd_ctx, "ERROR: last sector must be <= %d",
(int) num_sectors - 1);
return ERROR_FAIL;

@@ -616,7 +616,8 @@ static int handle_flash_erase_command(struct command_context_s *cmd_ctx,
return retval;
command_print(cmd_ctx, "erased sectors %i through %i "
"on flash bank %i in %s",
first, last, bank_nr, duration_text);
(int) first, (int) last, (int) bank_nr,
@@ -667,8 +668,8 @@ static int handle_flash_protect_command(struct command_context_s *cmd_ctx,
if (retval == ERROR_OK) {
command_print(cmd_ctx, "%s protection for sectors %i "
"through %i on flash bank %i",
(set) ? "set" : "cleared", first,
last, bank_nr);
(set) ? "set" : "cleared", (int) first,
(int) last, (int) bank_nr);

+ 15
- 13
src/flash/lpc2900.c View File

@@ -444,9 +444,9 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
uint8_t (*page)[FLASH_PAGE_SIZE] )
/* Only pages 4...7 are user writable */
if( (pagenum < 4) || (pagenum > 7) )
if ((pagenum < 4) || (pagenum > 7))
LOG_ERROR( "Refuse to burn index sector page %" PRIu32, pagenum );
LOG_ERROR("Refuse to burn index sector page %d", pagenum);

@@ -479,7 +479,7 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
bank->base + pagenum * FLASH_PAGE_SIZE,
4, FLASH_PAGE_SIZE / 4, (uint8_t *)page) != ERROR_OK )
LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
LOG_ERROR("Index sector write failed @ page %d", pagenum);
target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );

@@ -501,10 +501,10 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
/* Wait for the end of the write operation. If it's not over after one
* second, something went dreadfully wrong... :-(
if( lpc2900_wait_status( bank, INTSRC_END_OF_BURN, 1000 ) != ERROR_OK )
if (lpc2900_wait_status(bank, INTSRC_END_OF_BURN, 1000) != ERROR_OK)
LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
LOG_ERROR("Index sector write failed @ page %d", pagenum);
target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);

@@ -796,7 +796,8 @@ static int lpc2900_handle_write_custom_command( struct command_context_s *cmd_ct
if( (image.sections[0].base_address != 0) ||
(image.sections[0].size != ISS_CUSTOMER_SIZE) )
LOG_ERROR("Incorrect image file size. Expected %" PRIu32 ", got %" PRIu32,
LOG_ERROR("Incorrect image file size. Expected %d, "
"got %" PRIu32,
ISS_CUSTOMER_SIZE, image.sections[0].size);
@@ -1477,12 +1478,13 @@ static int lpc2900_write(struct flash_bank_s *bank, uint8_t *buffer,

/* Skip the current sector if it is secured */
if( bank->sectors[start_sector].is_protected )
if (bank->sectors[start_sector].is_protected)
LOG_DEBUG( "Skip secured sector %" PRIu32, start_sector );
LOG_DEBUG("Skip secured sector %d",

/* Stop if this is the last sector */
if( start_sector == bank->num_sectors - 1 )
if (start_sector == bank->num_sectors - 1)
@@ -1763,9 +1765,9 @@ static int lpc2900_probe(struct flash_bank_s *bank)

/* Show detected device */
LOG_INFO("Flash bank %" PRIu32
LOG_INFO("Flash bank %d"
": Device %s, %" PRIu32
" KiB in %" PRIu32 " sectors",
" KiB in %d sectors",
lpc2900_info->target_name, bank->size / KiB,
@@ -1805,7 +1807,7 @@ static int lpc2900_probe(struct flash_bank_s *bank)
* that has more than 19 sectors. Politely ask for a fix then.
bank->sectors[i].size = 0;
LOG_ERROR("Never heard about sector %" PRIu32 " (FIXME please)", i);
LOG_ERROR("Never heard about sector %d", i);

offset += bank->sectors[i].size;

+ 2
- 2
src/flash/mx3_nand.c View File

@@ -40,9 +40,9 @@ get_next_halfword_from_sram_buffer() not tested
static const char target_not_halted_err_msg[] =
"target must be halted to use mx3 NAND flash controller";
static const char data_block_size_err_msg[] =
"minimal granularity is one half-word, %d is incorrect";
"minimal granularity is one half-word, %" PRId32 " is incorrect";
static const char sram_buffer_bounds_err_msg[] =
"trying to access out of SRAM buffer bound (addr=0x%x)";
"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
static const char get_status_register_err_msg[] = "can't get NAND status";
static uint32_t in_sram_address;
unsigned char sign_of_sequental_byte_read;

+ 20
- 11
src/jtag/core.c View File

@@ -1167,7 +1167,7 @@ static int jtag_validate_ircapture(void)
(tap->ir_length + 7) / tap->ir_length,
(tap->ir_length + 7) / tap->ir_length,
(unsigned) tap->ir_capture_value);

goto done;
@@ -1360,22 +1360,31 @@ int jtag_init_reset(struct command_context_s *cmd_ctx)
if ((retval = jtag_interface_init(cmd_ctx)) != ERROR_OK)
return retval;

LOG_DEBUG("Trying to bring the JTAG controller to life by asserting TRST / TLR");
LOG_DEBUG("Initializing with hard TRST+SRST reset");

/* Reset can happen after a power cycle.
* Ideally we would only assert TRST or run TLR before the target reset.
* This procedure is used by default when OpenOCD triggers a reset.
* It's now done through an overridable Tcl "init_reset" wrapper.
* However w/srst_pulls_trst, trst is asserted together with the target
* reset whether we want it or not.
* This started out as a more powerful "get JTAG working" reset than
* jtag_init_inner(), applying TRST because some chips won't activate
* JTAG without a TRST cycle (presumed to be async, though some of
* those chips synchronize JTAG activation using TCK).
* NB! Some targets have JTAG circuitry disabled until a
* trst & srst has been asserted.
* But some chips only activate JTAG as part of an SRST cycle; SRST
* got mixed in. So it became a hard reset routine, which got used
* in more places, and which coped with JTAG reset being forced as
* part of SRST (srst_pulls_trst).
* NB! here we assume nsrst/ntrst delay are sufficient!
* And even more corner cases started to surface: TRST and/or SRST
* assertion timings matter; some chips need other JTAG operations;
* TRST/SRST sequences can need to be different from these, etc.
* NB! order matters!!!! srst *can* disconnect JTAG circuitry
* Systems should override that wrapper to support system-specific
* requirements that this not-fully-generic code doesn't handle.
* REVISIT once Tcl code can read the reset_config modes, this won't
* need to be a C routine at all...
jtag_add_reset(1, 0); /* TAP_RESET, using TMS+TCK or TRST */
if (jtag_reset_config & RESET_HAS_SRST)

+ 4
- 2
src/target/arm11.c View File

@@ -1480,8 +1480,10 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,

if (address + size * count != r0)
LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
address + size * count, r0);
LOG_ERROR("Data transfer failed. Expected end "
"address 0x%08x, got 0x%08x",
(unsigned) (address + size * count),
(unsigned) r0);

if (arm11_config_memwrite_burst)
LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");

+ 10
- 10
src/target/etm.c View File

@@ -1497,29 +1497,29 @@ static int handle_etm_info_command(struct command_context_s *cmd_ctx,
command_print(cmd_ctx, "ETM v%d.%d",
etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
command_print(cmd_ctx, "pairs of address comparators: %i",
(etm->config >> 0) & 0x0f);
(int) (etm->config >> 0) & 0x0f);
command_print(cmd_ctx, "data comparators: %i",
(etm->config >> 4) & 0x0f);
(int) (etm->config >> 4) & 0x0f);
command_print(cmd_ctx, "memory map decoders: %i",
(etm->config >> 8) & 0x1f);
(int) (etm->config >> 8) & 0x1f);
command_print(cmd_ctx, "number of counters: %i",
(etm->config >> 13) & 0x07);
(int) (etm->config >> 13) & 0x07);
command_print(cmd_ctx, "sequencer %spresent",
(etm->config & (1 << 16)) ? "" : "not ");
(int) (etm->config & (1 << 16)) ? "" : "not ");
command_print(cmd_ctx, "number of ext. inputs: %i",
(etm->config >> 17) & 0x07);
(int) (etm->config >> 17) & 0x07);
command_print(cmd_ctx, "number of ext. outputs: %i",
(etm->config >> 20) & 0x07);
(int) (etm->config >> 20) & 0x07);
command_print(cmd_ctx, "FIFO full %spresent",
(etm->config & (1 << 23)) ? "" : "not ");
(int) (etm->config & (1 << 23)) ? "" : "not ");
if (etm->bcd_vers < 0x20)
command_print(cmd_ctx, "protocol version: %i",
(etm->config >> 28) & 0x07);
(int) (etm->config >> 28) & 0x07);
else {
command_print(cmd_ctx, "trace start/stop %spresent",
(etm->config & (1 << 26)) ? "" : "not ");
command_print(cmd_ctx, "number of context comparators: %i",
(etm->config >> 24) & 0x03);
(int) (etm->config >> 24) & 0x03);

/* SYS_CONFIG isn't present before ETMv1.2 */

+ 243
- 244
File diff suppressed because it is too large
View File

+ 12
- 7
tcl/target/pxa270.cfg View File

@@ -12,14 +12,19 @@ if { [info exists ENDIAN] } {
set _ENDIAN little

#IDs for pxa270. Choose one. Are there others?#
#set CPUTAPID 0x79265013
#set CPUTAPID 0x49265013
#IDs for pxa270. Are there more?
if { [info exists CPUTAPID ] } {
} else {
# force an error till we get a good number
set _CPUTAPID 0xffffffff
# set useful default
set _CPUTAPID 0x49265013

if { [info exists CPUTAPID2 ] } {
} else {
# set useful default
set _CPUTAPID2 0x79265013

@@ -28,10 +33,10 @@ if { [info exists CPUTAPID ] } {
jtag_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 0
jtag_ntrst_delay 250

jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2

target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
# maps to PXA internal RAM. If you are using a PXA255