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@@ -9190,6 +9190,14 @@ Selects whether interrupts will be processed when single stepping. The default c |
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@option{on}. |
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@end deffn |
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@deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+ |
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Cause @command{$target_name} to halt when an exception is taken. Any combination of |
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Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target |
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@command{$target_name} will halt before taking the exception. In order to resume |
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the target, the exception catch must be disabled again with @command{$target_name catch_exc off}. |
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Issuing the command without options prints the current configuration. |
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@end deffn |
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@section EnSilica eSi-RISC Architecture |
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eSi-RISC is a highly configurable microprocessor architecture for embedded systems |
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@@ -9333,7 +9341,7 @@ collection. |
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@deffn Command {esirisc trace init} |
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Initialize trace collection. This command must be called any time the |
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configuration changes. If an trace buffer has been configured, the contents will |
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configuration changes. If a trace buffer has been configured, the contents will |
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be overwritten when trace collection starts. |
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@end deffn |
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@@ -9367,14 +9375,6 @@ be copied to an in-memory buffer identified by the @option{address} and |
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@option{size} options using DMA. |
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@end deffn |
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@deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+ |
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Cause @command{$target_name} to halt when an exception is taken. Any combination of |
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Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target |
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@command{$target_name} will halt before taking the exception. In order to resume |
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the target, the exception catch must be disabled again with @command{$target_name catch_exc off}. |
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Issuing the command without options prints the current configuration. |
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@end deffn |
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@section Intel Architecture |
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Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32 |
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