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@@ -93,11 +93,6 @@ struct mips32_pracc_context { |
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struct mips_ejtag *ejtag_info; |
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}; |
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static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, |
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uint32_t start_addr, uint32_t end_addr); |
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static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, |
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uint32_t start_addr, uint32_t end_addr); |
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static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) |
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{ |
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uint32_t ejtag_ctrl; |
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@@ -598,136 +593,116 @@ exit: |
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* to write back any containing D-cache line and invalidate any locations |
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* already in the I-cache. |
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* |
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* You can do that with cache instructions, but those instructions are only available in kernel mode, |
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* and a loader writing instructions for the use of its own process need not be privileged software. |
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* If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need |
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* to write back. |
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* |
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* In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, |
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* which does the whole job for a cache-line-sized chunk of the memory you just loaded: |
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* That is, it arranges a D-cache write-back and an I-cache invalidate. |
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* That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate. |
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* |
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* To employ synci at user level, you need to know the size of a cache line, |
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* and that can be obtained with a rdhwr SYNCI_Step |
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* from one of the standard “hardware registers”. |
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* The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1. |
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*/ |
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static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, |
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uint32_t start_addr, uint32_t end_addr) |
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static int mips32_pracc_synchronize_cache(struct mips_ejtag *ejtag_info, |
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uint32_t start_addr, uint32_t end_addr, int cached, int rel) |
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{ |
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static const uint32_t code[] = { |
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/* start: */ |
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MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ |
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MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ |
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MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), |
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MIPS32_SW(8, 0, 15), /* sw $8,($15) */ |
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MIPS32_SW(9, 0, 15), /* sw $9,($15) */ |
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MIPS32_SW(10, 0, 15), /* sw $10,($15) */ |
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MIPS32_SW(11, 0, 15), /* sw $11,($15) */ |
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MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ |
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MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), |
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MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */ |
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MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */ |
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MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */ |
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MIPS32_BEQ(11, 0, 6), /* beq $11, $0, end */ |
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MIPS32_NOP, |
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/* synci_loop : */ |
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MIPS32_SYNCI(0, 9), /* synci 0($9) */ |
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MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */ |
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MIPS32_BNE(8, 0, NEG16(3)), /* bne $8, $0, synci_loop */ |
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MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */ |
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MIPS32_SYNC, |
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/* end: */ |
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MIPS32_LW(11, 0, 15), /* lw $11,($15) */ |
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MIPS32_LW(10, 0, 15), /* lw $10,($15) */ |
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MIPS32_LW(9, 0, 15), /* lw $9,($15) */ |
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MIPS32_LW(8, 0, 15), /* lw $8,($15) */ |
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MIPS32_B(NEG16(24)), /* b start */ |
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MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ |
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}; |
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struct pracc_queue_info ctx = {.max_code = 256 * 2 + 6}; |
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pracc_queue_init(&ctx); |
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if (ctx.retval != ERROR_OK) |
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goto exit; |
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/** Find cache line size in bytes */ |
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uint32_t clsiz; |
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if (rel) { /* Release 2 (rel = 1) */ |
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pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */ |
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pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ |
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/* TODO remove array */ |
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uint32_t *param_in = malloc(2 * sizeof(uint32_t)); |
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int retval; |
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param_in[0] = start_addr; |
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param_in[1] = end_addr; |
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pracc_add(&ctx, 0, MIPS32_RDHWR(8, MIPS32_SYNCI_STEP)); /* load synci_step value to $8 */ |
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retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 2, param_in, 0, NULL, 1); |
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pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, |
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MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */ |
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free(param_in); |
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pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */ |
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pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */ |
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pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ |
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pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */ |
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return retval; |
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} |
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, &clsiz); |
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if (ctx.retval != ERROR_OK) |
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goto exit; |
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/** |
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* \b mips32_pracc_clean_invalidate_cache |
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* |
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* Writeback D$ and Invalidate I$ |
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* so that the instructions written can be visible to CPU |
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*/ |
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static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, |
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uint32_t start_addr, uint32_t end_addr) |
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{ |
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static const uint32_t code[] = { |
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/* start: */ |
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MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ |
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MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ |
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MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), |
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MIPS32_SW(8, 0, 15), /* sw $8,($15) */ |
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MIPS32_SW(9, 0, 15), /* sw $9,($15) */ |
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MIPS32_SW(10, 0, 15), /* sw $10,($15) */ |
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MIPS32_SW(11, 0, 15), /* sw $11,($15) */ |
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MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ |
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MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), |
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MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */ |
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MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */ |
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MIPS32_LW(11, 8, 8), /* Load write clsiz to $11 */ |
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/* cache_loop: */ |
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MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */ |
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MIPS32_BGTZ(8, 6), /* bgtz $8, end */ |
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MIPS32_NOP, |
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} else { /* Release 1 (rel = 0) */ |
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uint32_t conf; |
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ctx.retval = mips32_cp0_read(ejtag_info, &conf, 16, 1); |
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if (ctx.retval != ERROR_OK) |
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goto exit; |
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MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK, 0, 9), /* cache Hit_Writeback_D, 0($9) */ |
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MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE, 0, 9), /* cache Hit_Invalidate_I, 0($9) */ |
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uint32_t dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT; |
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MIPS32_ADDU(9, 9, 11), /* $9 += $11 */ |
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/* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... max dl=6 => 128 bytes cache line size */ |
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clsiz = 0x2 << dl; |
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if (dl == 0) |
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clsiz = 0; |
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} |
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MIPS32_B(NEG16(7)), /* b cache_loop */ |
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MIPS32_NOP, |
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/* end: */ |
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MIPS32_LW(11, 0, 15), /* lw $11,($15) */ |
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MIPS32_LW(10, 0, 15), /* lw $10,($15) */ |
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MIPS32_LW(9, 0, 15), /* lw $9,($15) */ |
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MIPS32_LW(8, 0, 15), /* lw $8,($15) */ |
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MIPS32_B(NEG16(25)), /* b start */ |
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MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ |
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}; |
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if (clsiz == 0) |
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goto exit; /* Nothing to do */ |
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/** |
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* Find cache line size in bytes |
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*/ |
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uint32_t conf; |
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uint32_t dl, clsiz; |
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/* make sure clsiz is power of 2 */ |
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if (clsiz & (clsiz - 1)) { |
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LOG_DEBUG("clsiz must be power of 2"); |
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ctx.retval = ERROR_FAIL; |
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goto exit; |
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} |
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mips32_cp0_read(ejtag_info, &conf, 16, 1); |
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dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT; |
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/* make sure start_addr and end_addr have the same offset inside de cache line */ |
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start_addr |= clsiz - 1; |
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end_addr |= clsiz - 1; |
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/* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... */ |
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clsiz = 0x2 << dl; |
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ctx.code_count = 0; |
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int count = 0; |
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uint32_t last_upper_base_addr = UPPER16((start_addr + 0x8000)); |
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/* TODO remove array */ |
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uint32_t *param_in = malloc(3 * sizeof(uint32_t)); |
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int retval; |
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param_in[0] = start_addr; |
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param_in[1] = end_addr; |
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param_in[2] = clsiz; |
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pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */ |
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pracc_add(&ctx, 0, MIPS32_LUI(15, last_upper_base_addr)); /* load upper memory base address to $15 */ |
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while (start_addr <= end_addr) { /* main loop */ |
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uint32_t upper_base_addr = UPPER16((start_addr + 0x8000)); |
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if (last_upper_base_addr != upper_base_addr) { /* if needed, change upper address in $15 */ |
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pracc_add(&ctx, 0, MIPS32_LUI(15, upper_base_addr)); |
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last_upper_base_addr = upper_base_addr; |
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} |
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if (rel) |
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pracc_add(&ctx, 0, MIPS32_SYNCI(LOWER16(start_addr), 15)); /* synci instruction, offset($15) */ |
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retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 3, param_in, 0, NULL, 1); |
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else { |
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if (cached == 3) |
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pracc_add(&ctx, 0, MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK, |
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LOWER16(start_addr), 15)); /* cache Hit_Writeback_D, offset($15) */ |
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free(param_in); |
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pracc_add(&ctx, 0, MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE, |
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LOWER16(start_addr), 15)); /* cache Hit_Invalidate_I, offset($15) */ |
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} |
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start_addr += clsiz; |
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count++; |
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if (count == 256 && start_addr <= end_addr) { /* more ?, then execute code list */ |
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pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ |
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pracc_add(&ctx, 0, MIPS32_NOP); /* nop in delay slot */ |
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return retval; |
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); |
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if (ctx.retval != ERROR_OK) |
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goto exit; |
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ctx.code_count = 0; |
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count = 0; |
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} |
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} |
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pracc_add(&ctx, 0, MIPS32_SYNC); |
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pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ |
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pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave*/ |
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); |
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exit: |
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pracc_queue_free(&ctx); |
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return ctx.retval; |
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} |
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static int mips32_pracc_write_mem_generic(struct mips_ejtag *ejtag_info, |
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@@ -806,9 +781,9 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz |
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return retval; |
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/** |
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* If we are in the cachable regoion and cache is activated, |
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* we must clean D$ + invalidate I$ after we did the write, |
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* so that changes do not continue to live only in D$, but to be |
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* If we are in the cacheable region and cache is activated, |
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* we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write, |
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* so that changes do not continue to live only in D$ (if CCA = 3), but to be |
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* replicated in I$ also (maybe we wrote the istructions) |
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*/ |
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uint32_t conf = 0; |
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@@ -836,32 +811,19 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz |
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} |
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/** |
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* Check cachablitiy bits coherency algorithm - |
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* Check cachablitiy bits coherency algorithm |
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* is the region cacheable or uncached. |
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* If cacheable we have to synchronize the cache |
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*/ |
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if (cached == 0x3) { |
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uint32_t start_addr, end_addr; |
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uint32_t rel; |
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start_addr = addr; |
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end_addr = addr + count * size; |
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/** select cache synchronisation mechanism based on Architecture Release */ |
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rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; |
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switch (rel) { |
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case MIPS32_ARCH_REL1: |
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/* MIPS32/64 Release 1 - we must use cache instruction */ |
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mips32_pracc_clean_invalidate_cache(ejtag_info, start_addr, end_addr); |
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break; |
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case MIPS32_ARCH_REL2: |
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/* MIPS32/64 Release 2 - we can use synci instruction */ |
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mips32_pracc_sync_cache(ejtag_info, start_addr, end_addr); |
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break; |
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default: |
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/* what ? */ |
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break; |
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if (cached == 3 || cached == 0) { /* Write back cache or write through cache */ |
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uint32_t start_addr = addr; |
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uint32_t end_addr = addr + count * size; |
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uint32_t rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; |
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if (rel > 1) { |
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LOG_DEBUG("Unknown release in cache code"); |
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return ERROR_FAIL; |
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} |
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retval = mips32_pracc_synchronize_cache(ejtag_info, start_addr, end_addr, cached, rel); |
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} |
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return retval; |
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