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@@ -1332,6 +1332,8 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, |
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exit(-1); |
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} |
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if (target->state == TARGET_HALTED) |
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{ |
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/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ |
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/* invalidate I-Cache */ |
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if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) |
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@@ -1349,6 +1351,7 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, |
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for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) |
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armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ |
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} |
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} |
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return retval; |
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} |
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