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@@ -617,6 +617,90 @@ static int jim_arm946e_cp15(Jim_Interp *interp, int argc, Jim_Obj * const *argv) |
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return JIM_OK; |
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} |
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COMMAND_HANDLER(arm946e_handle_idcache) |
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{ |
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if (CMD_ARGC > 1) |
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return ERROR_COMMAND_SYNTAX_ERROR; |
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int retval; |
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struct target *target = get_current_target(CMD_CTX); |
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struct arm946e_common *arm946e = target_to_arm946(target); |
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retval = arm946e_verify_pointer(CMD_CTX, arm946e); |
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if (retval != ERROR_OK) |
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return retval; |
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if (target->state != TARGET_HALTED) { |
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command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); |
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return ERROR_TARGET_NOT_HALTED; |
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} |
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bool icache = (strcmp(CMD_NAME, "icache") == 0); |
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uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024; |
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if (CMD_ARGC == 0) { |
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bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0) |
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&& (arm946e->cp15_control_reg & 0x1); |
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if (csize == 0) |
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command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D"); |
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else |
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command_print(CMD_CTX, "%s-cache size: %dK, %s", icache ? "I" : "D", csize, bena ? "enabled" : "disabled"); |
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return ERROR_OK; |
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} |
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bool flush = false; |
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bool enable = false; |
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retval = command_parse_bool_arg(CMD_ARGV[0], &enable); |
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if (retval == ERROR_COMMAND_SYNTAX_ERROR) { |
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if (strcmp(CMD_ARGV[0], "flush") == 0) { |
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flush = true; |
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retval = ERROR_OK; |
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} else |
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return retval; |
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} |
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/* Do not invalidate or change state, if cache is absent */ |
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if (csize == 0) { |
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command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]); |
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; |
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} |
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/* NOTE: flushing entire cache will not preserve lock-down cache regions */ |
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if (icache) { |
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if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable) |
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retval = arm946e_invalidate_whole_icache(target); |
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} else { |
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if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable) |
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retval = arm946e_invalidate_whole_dcache(target); |
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} |
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if (retval != ERROR_OK || flush) |
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return retval; |
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uint32_t value; |
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retval = arm946e_read_cp15(target, CP15_CTL, &value); |
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if (retval != ERROR_OK) |
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return retval; |
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uint32_t vnew = value; |
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uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE; |
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if (enable) { |
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if ((value & 0x1) == 0) |
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LOG_WARNING("arm946e: MPU must be enabled for cache to operate"); |
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vnew |= cmask; |
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} else |
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vnew &= ~cmask; |
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if (vnew == value) |
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return ERROR_OK; |
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retval = arm946e_write_cp15(target, CP15_CTL, vnew); |
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if (retval != ERROR_OK) |
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return retval; |
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arm946e_update_cp15_caches(target, vnew); |
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return ERROR_OK; |
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} |
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static const struct command_registration arm946e_exec_command_handlers[] = { |
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{ |
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.name = "cp15", |
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@@ -625,6 +709,20 @@ static const struct command_registration arm946e_exec_command_handlers[] = { |
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.usage = "regnum [value]", |
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.help = "read/modify cp15 register", |
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}, |
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{ |
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.name = "icache", |
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.handler = arm946e_handle_idcache, |
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.mode = COMMAND_EXEC, |
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.usage = "['enable'|'disable'|'flush']", |
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.help = "I-cache info and operations", |
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}, |
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{ |
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.name = "dcache", |
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.handler = arm946e_handle_idcache, |
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.mode = COMMAND_EXEC, |
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.usage = "['enable'|'disable'|'flush']", |
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.help = "D-cache info and operations", |
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}, |
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COMMAND_REGISTRATION_DONE |
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}; |
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