- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>jim-nrf5-free
@@ -4002,6 +4002,84 @@ with these TAPs, any targets associated with them, and any on-chip | |||
resources; then a @file{board.cfg} with off-chip resources, clocking, | |||
and so forth. | |||
@anchor{dapdeclaration} | |||
@section DAP declaration (ARMv7 and ARMv8 targets) | |||
@cindex DAP declaration | |||
Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is | |||
no longer implicitly created together with the target. It must be | |||
explicitly declared using the @command{dap create} command. For all | |||
ARMv7 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used | |||
instead of "@option{-chain-position} @var{dotted.name}" when the target is created. | |||
The @command{dap} command group supports the following sub-commands: | |||
@deffn Command {dap create} dap_name @option{-chain-position} dotted.name | |||
Declare a DAP instance named @var{dap_name} linked to the JTAG tap | |||
@var{dotted.name}. This also creates a new command (@command{dap_name}) | |||
which is used for various purposes including additional configuration. | |||
There can only be one DAP for each JTAG tap in the system. | |||
@end deffn | |||
@deffn Command {dap names} | |||
This command returns a list of all registered DAP objects. It it useful mainly | |||
for TCL scripting. | |||
@end deffn | |||
@deffn Command {dap info} [num] | |||
Displays the ROM table for MEM-AP @var{num}, | |||
defaulting to the currently selected AP of the currently selected target. | |||
@end deffn | |||
@deffn Command {dap init} | |||
Initialize all registered DAPs. This command is used internally | |||
during initialization. It can be issued at any time after the | |||
initialization, too. | |||
@end deffn | |||
The following commands exist as subcommands of DAP instances: | |||
@deffn Command {$dap_name info} [num] | |||
Displays the ROM table for MEM-AP @var{num}, | |||
defaulting to the currently selected AP. | |||
@end deffn | |||
@deffn Command {$dap_name apid} [num] | |||
Displays ID register from AP @var{num}, defaulting to the currently selected AP. | |||
@end deffn | |||
@deffn Command {$dap_name apreg} ap_num reg [value] | |||
Displays content of a register @var{reg} from AP @var{ap_num} | |||
or set a new value @var{value}. | |||
@var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc. | |||
@end deffn | |||
@deffn Command {$dap_name apsel} [num] | |||
Select AP @var{num}, defaulting to 0. | |||
@end deffn | |||
@deffn Command {$dap_name baseaddr} [num] | |||
Displays debug base address from MEM-AP @var{num}, | |||
defaulting to the currently selected AP. | |||
@end deffn | |||
@deffn Command {$dap_name memaccess} [value] | |||
Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP | |||
memory bus access [0-255], giving additional time to respond to reads. | |||
If @var{value} is defined, first assigns that. | |||
@end deffn | |||
@deffn Command {$dap_name apcsw} [0 / 1] | |||
fix CSW_SPROT from register AP_REG_CSW on selected dap. | |||
Defaulting to 0. | |||
@end deffn | |||
@deffn Command {$dap_name ti_be_32_quirks} [@option{enable}] | |||
Set/get quirks mode for TI TMS450/TMS570 processors | |||
Disabled by default | |||
@end deffn | |||
@node CPU Configuration | |||
@chapter CPU Configuration | |||
@cindex GDB target | |||
@@ -4168,10 +4246,11 @@ to be much more board-specific. | |||
The key steps you use might look something like this | |||
@example | |||
target create MyTarget cortex_m -chain-position mychip.cpu | |||
$MyTarget configure -work-area-phys 0x08000 -work-area-size 8096 | |||
$MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @} | |||
$MyTarget configure -event reset-init @{ myboard_reinit @} | |||
dap create mychip.dap -chain-position mychip.cpu | |||
target create MyTarget cortex_m -dap mychip.dap | |||
MyTarget configure -work-area-phys 0x08000 -work-area-size 8096 | |||
MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @} | |||
MyTarget configure -event reset-init @{ myboard_reinit @} | |||
@end example | |||
You should specify a working area if you can; typically it uses some | |||
@@ -4221,7 +4300,8 @@ and in other places the target needs to be identified. | |||
@command{$target_name configure} are permitted. | |||
If the target is big-endian, set it here with @code{-endian big}. | |||
You @emph{must} set the @code{-chain-position @var{dotted.name}} here. | |||
You @emph{must} set the @code{-chain-position @var{dotted.name}} or | |||
@code{-dap @var{dap_name}} here. | |||
@end itemize | |||
@end deffn | |||
@@ -4240,6 +4320,10 @@ and changing its endianness. | |||
@item @code{-chain-position} @var{dotted.name} -- names the TAP | |||
used to access this target. | |||
@item @code{-dap} @var{dap_name} -- names the DAP used to access | |||
this target. @xref{dapdeclaration,,DAP declaration}, on how to | |||
create and manage DAP instances. | |||
@item @code{-endian} (@option{big}|@option{little}) -- specifies | |||
whether the CPU uses big or little endian conventions | |||
@@ -7794,12 +7878,12 @@ CTI is mandatory for core run control and each core has an individual | |||
CTI instance attached to it. OpenOCD has limited support for CTI using | |||
the @emph{cti} group of commands. | |||
@deffn Command {cti create} @var{cti_name} -chain-position @var{tap_name} -ap-num @var{apn} -ctibase @var{base_address} | |||
Creates a CTI object @var{cti_name} on the JTAG tap @var{tap_name} on MEM-AP | |||
@var{apn} of the DAP reachable through @var{tap}. The @var{base_address} must match | |||
the base address of the CTI on the respective MEM-AP. All arguments are | |||
mandatory. This creates a new command (@command{@var{cti_name}}) which | |||
is used for various purposes including additional configuration. | |||
@deffn Command {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-ctibase} base_address | |||
Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP | |||
@var{apn}. The @var{base_address} must match the base address of the CTI | |||
on the respective MEM-AP. All arguments are mandatory. This creates a | |||
new command @command{$cti_name} which is used for various purposes | |||
including additional configuration. | |||
@end deffn | |||
@deffn Command {$cti_name enable} @option{on|off} | |||
@@ -8306,55 +8390,6 @@ cores @emph{except the ARM1176} use the same six bits. | |||
@cindex ARMv7 | |||
@cindex ARMv8 | |||
@subsection ARMv7 and ARMv8 Debug Access Port (DAP) specific commands | |||
@cindex Debug Access Port | |||
@cindex DAP | |||
These commands are specific to ARM architecture v7 and v8 Debug Access Port (DAP), | |||
included on Cortex-M and Cortex-A systems. | |||
They are available in addition to other core-specific commands that may be available. | |||
@deffn Command {dap apid} [num] | |||
Displays ID register from AP @var{num}, | |||
defaulting to the currently selected AP. | |||
@end deffn | |||
@deffn Command {dap apreg} ap_num reg [value] | |||
Displays content of a register @var{reg} from AP @var{ap_num} | |||
or set a new value @var{value}. | |||
@var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc. | |||
@end deffn | |||
@deffn Command {dap apsel} [num] | |||
Select AP @var{num}, defaulting to 0. | |||
@end deffn | |||
@deffn Command {dap baseaddr} [num] | |||
Displays debug base address from MEM-AP @var{num}, | |||
defaulting to the currently selected AP. | |||
@end deffn | |||
@deffn Command {dap info} [num] | |||
Displays the ROM table for MEM-AP @var{num}, | |||
defaulting to the currently selected AP. | |||
@end deffn | |||
@deffn Command {dap memaccess} [value] | |||
Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP | |||
memory bus access [0-255], giving additional time to respond to reads. | |||
If @var{value} is defined, first assigns that. | |||
@end deffn | |||
@deffn Command {dap apcsw} [0 / 1] | |||
fix CSW_SPROT from register AP_REG_CSW on selected dap. | |||
Defaulting to 0. | |||
@end deffn | |||
@deffn Command {dap ti_be_32_quirks} [@option{enable}] | |||
Set/get quirks mode for TI TMS450/TMS570 processors | |||
Disabled by default | |||
@end deffn | |||
@subsection ARMv7-A specific commands | |||
@cindex Cortex-A | |||
@@ -1315,7 +1315,6 @@ void jtag_tap_free(struct jtag_tap *tap) | |||
free(tap->chip); | |||
free(tap->tapname); | |||
free(tap->dotted_name); | |||
free(tap->dap); | |||
free(tap); | |||
} | |||
@@ -1487,6 +1486,8 @@ int adapter_quit(void) | |||
t = n; | |||
} | |||
dap_cleanup_all(); | |||
return ERROR_OK; | |||
} | |||
@@ -153,8 +153,6 @@ struct jtag_tap { | |||
struct jtag_tap_event_action *event_action; | |||
struct jtag_tap *next_tap; | |||
/* dap instance if some null if no instance , initialized to 0 by calloc*/ | |||
struct adiv5_dap *dap; | |||
/* private pointer to support none-jtag specific functions */ | |||
void *priv; | |||
}; | |||
@@ -38,6 +38,7 @@ | |||
#include <pld/pld.h> | |||
#include <flash/mflash.h> | |||
#include <target/arm_cti.h> | |||
#include <target/arm_adi_v5.h> | |||
#include <server/server.h> | |||
#include <server/gdb_server.h> | |||
@@ -151,6 +152,10 @@ COMMAND_HANDLER(handle_init_command) | |||
if (ERROR_OK != retval) | |||
return ERROR_FAIL; | |||
retval = command_run_line(CMD_CTX, "dap init"); | |||
if (ERROR_OK != retval) | |||
return ERROR_FAIL; | |||
LOG_DEBUG("Examining targets..."); | |||
if (target_examine() != ERROR_OK) | |||
LOG_DEBUG("target examination failed"); | |||
@@ -254,6 +259,7 @@ struct command_context *setup_command_handler(Jim_Interp *interp) | |||
&pld_register_commands, | |||
&mflash_register_commands, | |||
&cti_register_commands, | |||
&dap_register_commands, | |||
NULL | |||
}; | |||
for (unsigned i = 0; NULL != command_registrants[i]; i++) { | |||
@@ -88,6 +88,7 @@ ARM_DEBUG_SRC = \ | |||
%D%/arm_simulator.c \ | |||
%D%/arm_semihosting.c \ | |||
%D%/arm_adi_v5.c \ | |||
%D%/arm_dap.c \ | |||
%D%/armv7a_cache.c \ | |||
%D%/armv7a_cache_l2x.c \ | |||
%D%/adi_v5_jtag.c \ | |||
@@ -41,6 +41,7 @@ enum halt_mode { | |||
}; | |||
struct aarch64_private_config { | |||
struct adiv5_private_config adiv5_config; | |||
struct arm_cti *cti; | |||
}; | |||
@@ -2210,10 +2211,6 @@ static int aarch64_examine_first(struct target *target) | |||
uint32_t tmp0, tmp1, tmp2, tmp3; | |||
debug = ttypr = cpuid = 0; | |||
retval = dap_dp_init(swjdp); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
/* Search for the APB-AB - it is needed for access to debug registers */ | |||
retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap); | |||
if (retval != ERROR_OK) { | |||
@@ -2358,18 +2355,13 @@ static int aarch64_init_target(struct command_context *cmd_ctx, | |||
} | |||
static int aarch64_init_arch_info(struct target *target, | |||
struct aarch64_common *aarch64, struct jtag_tap *tap) | |||
struct aarch64_common *aarch64, struct adiv5_dap *dap) | |||
{ | |||
struct armv8_common *armv8 = &aarch64->armv8_common; | |||
/* Setup struct aarch64_common */ | |||
aarch64->common_magic = AARCH64_COMMON_MAGIC; | |||
/* tap has no dap initialized */ | |||
if (!tap->dap) { | |||
tap->dap = dap_init(); | |||
tap->dap->tap = tap; | |||
} | |||
armv8->arm.dap = tap->dap; | |||
armv8->arm.dap = dap; | |||
/* register arch-specific functions */ | |||
armv8->examine_debug_reason = NULL; | |||
@@ -2385,9 +2377,13 @@ static int aarch64_init_arch_info(struct target *target, | |||
static int aarch64_target_create(struct target *target, Jim_Interp *interp) | |||
{ | |||
struct aarch64_private_config *pc = target->private_config; | |||
struct aarch64_common *aarch64 = calloc(1, sizeof(struct aarch64_common)); | |||
return aarch64_init_arch_info(target, aarch64, target->tap); | |||
if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK) | |||
return ERROR_FAIL; | |||
return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap); | |||
} | |||
static int aarch64_mmu(struct target *target, int *enabled) | |||
@@ -2407,58 +2403,89 @@ static int aarch64_virt2phys(struct target *target, target_addr_t virt, | |||
return armv8_mmu_translate_va_pa(target, virt, phys, 1); | |||
} | |||
/* | |||
* private target configuration items | |||
*/ | |||
enum aarch64_cfg_param { | |||
CFG_CTI, | |||
}; | |||
static const Jim_Nvp nvp_config_opts[] = { | |||
{ .name = "-cti", .value = CFG_CTI }, | |||
{ .name = NULL, .value = -1 } | |||
}; | |||
static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi) | |||
{ | |||
struct aarch64_private_config *pc; | |||
const char *arg; | |||
Jim_Nvp *n; | |||
int e; | |||
/* check if argv[0] is for us */ | |||
arg = Jim_GetString(goi->argv[0], NULL); | |||
if (strcmp(arg, "-cti")) | |||
return JIM_CONTINUE; | |||
pc = (struct aarch64_private_config *)target->private_config; | |||
if (pc == NULL) { | |||
pc = calloc(1, sizeof(struct aarch64_private_config)); | |||
target->private_config = pc; | |||
} | |||
/* pop the argument from argv */ | |||
e = Jim_GetOpt_String(goi, &arg, NULL); | |||
if (e != JIM_OK) | |||
/* | |||
* Call adiv5_jim_configure() to parse the common DAP options | |||
* It will return JIM_CONTINUE if it didn't find any known | |||
* options, JIM_OK if it correctly parsed the topmost option | |||
* and JIM_ERR if an error occured during parameter evaluation. | |||
* For JIM_CONTINUE, we check our own params. | |||
*/ | |||
e = adiv5_jim_configure(target, goi); | |||
if (e != JIM_CONTINUE) | |||
return e; | |||
/* check if we have another option */ | |||
if (goi->argc == 0) { | |||
Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-cti ?cti-name?"); | |||
return JIM_ERR; | |||
} | |||
/* parse config or cget options ... */ | |||
if (goi->argc > 0) { | |||
Jim_SetEmptyResult(goi->interp); | |||
pc = (struct aarch64_private_config *)target->private_config; | |||
/* check first if topmost item is for us */ | |||
e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts, | |||
goi->argv[0], &n); | |||
if (e != JIM_OK) | |||
return JIM_CONTINUE; | |||
if (goi->isconfigure) { | |||
Jim_Obj *o_cti; | |||
struct arm_cti *cti; | |||
e = Jim_GetOpt_Obj(goi, &o_cti); | |||
e = Jim_GetOpt_Obj(goi, NULL); | |||
if (e != JIM_OK) | |||
return e; | |||
cti = cti_instance_by_jim_obj(goi->interp, o_cti); | |||
if (cti == NULL) | |||
return JIM_ERR; | |||
if (pc == NULL) { | |||
pc = calloc(1, sizeof(struct aarch64_private_config)); | |||
target->private_config = pc; | |||
} | |||
pc->cti = cti; | |||
} else { | |||
if (goi->argc != 0) { | |||
Jim_WrongNumArgs(goi->interp, | |||
goi->argc, goi->argv, | |||
"NO PARAMS"); | |||
return JIM_ERR; | |||
switch (n->value) { | |||
case CFG_CTI: { | |||
if (goi->isconfigure) { | |||
Jim_Obj *o_cti; | |||
struct arm_cti *cti; | |||
e = Jim_GetOpt_Obj(goi, &o_cti); | |||
if (e != JIM_OK) | |||
return e; | |||
cti = cti_instance_by_jim_obj(goi->interp, o_cti); | |||
if (cti == NULL) { | |||
Jim_SetResultString(goi->interp, "CTI name invalid!", -1); | |||
return JIM_ERR; | |||
} | |||
pc->cti = cti; | |||
} else { | |||
if (goi->argc != 0) { | |||
Jim_WrongNumArgs(goi->interp, | |||
goi->argc, goi->argv, | |||
"NO PARAMS"); | |||
return JIM_ERR; | |||
} | |||
if (pc == NULL || pc->cti == NULL) { | |||
Jim_SetResultString(goi->interp, "CTI not configured", -1); | |||
return JIM_ERR; | |||
} | |||
Jim_SetResultString(goi->interp, arm_cti_name(pc->cti), -1); | |||
} | |||
break; | |||
} | |||
if (pc == NULL || pc->cti == NULL) { | |||
Jim_SetResultString(goi->interp, "CTI not configured", -1); | |||
return JIM_ERR; | |||
default: | |||
return JIM_CONTINUE; | |||
} | |||
Jim_SetResultString(goi->interp, arm_cti_name(pc->cti), -1); | |||
} | |||
return JIM_OK; | |||
@@ -574,6 +574,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) | |||
if ((ctrlstat & (CDBGPWRUPREQ | CDBGPWRUPACK | CSYSPWRUPREQ | CSYSPWRUPACK)) != | |||
(CDBGPWRUPREQ | CDBGPWRUPACK | CSYSPWRUPREQ | CSYSPWRUPACK)) { | |||
LOG_ERROR("Debug regions are unpowered, an unexpected reset might have happened"); | |||
dap->do_reconnect = true; | |||
} | |||
if (ctrlstat & SSTICKYERR) | |||
@@ -598,6 +599,20 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) | |||
/*--------------------------------------------------------------------------*/ | |||
static int jtag_connect(struct adiv5_dap *dap) | |||
{ | |||
dap->do_reconnect = false; | |||
return dap_dp_init(dap); | |||
} | |||
static int jtag_check_reconnect(struct adiv5_dap *dap) | |||
{ | |||
if (dap->do_reconnect) | |||
return jtag_connect(dap); | |||
return ERROR_OK; | |||
} | |||
static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg, | |||
uint32_t *data) | |||
{ | |||
@@ -633,7 +648,11 @@ static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg) | |||
static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg, | |||
uint32_t *data) | |||
{ | |||
int retval = jtag_ap_q_bankselect(ap, reg); | |||
int retval = jtag_check_reconnect(ap->dap); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
retval = jtag_ap_q_bankselect(ap, reg); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
@@ -647,7 +666,11 @@ static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg, | |||
static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg, | |||
uint32_t data) | |||
{ | |||
int retval = jtag_ap_q_bankselect(ap, reg); | |||
int retval = jtag_check_reconnect(ap->dap); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
retval = jtag_ap_q_bankselect(ap, reg); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
@@ -692,6 +715,7 @@ static int jtag_dp_sync(struct adiv5_dap *dap) | |||
* part of DAP setup | |||
*/ | |||
const struct dap_ops jtag_dp_ops = { | |||
.connect = jtag_connect, | |||
.queue_dp_read = jtag_dp_q_read, | |||
.queue_dp_write = jtag_dp_q_write, | |||
.queue_ap_read = jtag_ap_q_read, | |||
@@ -53,13 +53,11 @@ | |||
#include <jtag/swd.h> | |||
/* YUK! - but this is currently a global.... */ | |||
extern struct jtag_interface *jtag_interface; | |||
static bool do_sync; | |||
static void swd_finish_read(struct adiv5_dap *dap) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
if (dap->last_read != NULL) { | |||
swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0); | |||
dap->last_read = NULL; | |||
@@ -73,7 +71,7 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, | |||
static void swd_clear_sticky_errors(struct adiv5_dap *dap) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
assert(swd); | |||
swd->write_reg(swd_cmd(false, false, DP_ABORT), | |||
@@ -82,7 +80,7 @@ static void swd_clear_sticky_errors(struct adiv5_dap *dap) | |||
static int swd_run_inner(struct adiv5_dap *dap) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
int retval; | |||
retval = swd->run(); | |||
@@ -97,6 +95,7 @@ static int swd_run_inner(struct adiv5_dap *dap) | |||
static int swd_connect(struct adiv5_dap *dap) | |||
{ | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
uint32_t dpidr; | |||
int status; | |||
@@ -120,7 +119,7 @@ static int swd_connect(struct adiv5_dap *dap) | |||
} | |||
/* Note, debugport_init() does setup too */ | |||
jtag_interface->swd->switch_seq(JTAG_TO_SWD); | |||
swd->switch_seq(JTAG_TO_SWD); | |||
/* Clear link state, including the SELECT cache. */ | |||
dap->do_reconnect = false; | |||
@@ -136,6 +135,7 @@ static int swd_connect(struct adiv5_dap *dap) | |||
if (status == ERROR_OK) { | |||
LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr); | |||
dap->do_reconnect = false; | |||
status = dap_dp_init(dap); | |||
} else | |||
dap->do_reconnect = true; | |||
@@ -157,7 +157,7 @@ static int swd_check_reconnect(struct adiv5_dap *dap) | |||
static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
assert(swd); | |||
swd->write_reg(swd_cmd(false, false, DP_ABORT), | |||
@@ -187,7 +187,7 @@ static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg) | |||
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, | |||
uint32_t *data) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
assert(swd); | |||
int retval = swd_check_reconnect(dap); | |||
@@ -203,7 +203,7 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, | |||
static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg, | |||
uint32_t data) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
assert(swd); | |||
int retval = swd_check_reconnect(dap); | |||
@@ -236,10 +236,9 @@ static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg) | |||
static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg, | |||
uint32_t *data) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
assert(swd); | |||
struct adiv5_dap *dap = ap->dap; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
assert(swd); | |||
int retval = swd_check_reconnect(dap); | |||
if (retval != ERROR_OK) | |||
@@ -255,10 +254,9 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg, | |||
static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg, | |||
uint32_t data) | |||
{ | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
assert(swd); | |||
struct adiv5_dap *dap = ap->dap; | |||
const struct swd_driver *swd = adiv5_dap_swd_driver(dap); | |||
assert(swd); | |||
int retval = swd_check_reconnect(dap); | |||
if (retval != ERROR_OK) | |||
@@ -279,6 +277,7 @@ static int swd_run(struct adiv5_dap *dap) | |||
} | |||
const struct dap_ops swd_dap_ops = { | |||
.connect = swd_connect, | |||
.queue_dp_read = swd_queue_dp_read, | |||
.queue_dp_write = swd_queue_dp_write, | |||
.queue_ap_read = swd_queue_ap_read, | |||
@@ -381,15 +380,15 @@ static const struct command_registration swd_handlers[] = { | |||
static int swd_select(struct command_context *ctx) | |||
{ | |||
/* FIXME: only place where global 'jtag_interface' is still needed */ | |||
extern struct jtag_interface *jtag_interface; | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
int retval; | |||
retval = register_commands(ctx, NULL, swd_handlers); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
const struct swd_driver *swd = jtag_interface->swd; | |||
/* be sure driver is in SWD mode; start | |||
* with hardware default TRN (1), it can be changed later | |||
*/ | |||
@@ -404,33 +403,14 @@ static int swd_select(struct command_context *ctx) | |||
return retval; | |||
} | |||
/* force DAP into SWD mode (not JTAG) */ | |||
/*retval = dap_to_swd(target);*/ | |||
if (ctx->current_target) { | |||
/* force DAP into SWD mode (not JTAG) */ | |||
struct target *target = get_current_target(ctx); | |||
retval = dap_to_swd(target); | |||
} | |||
return retval; | |||
} | |||
static int swd_init(struct command_context *ctx) | |||
{ | |||
struct target *target = get_current_target(ctx); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
/* Force the DAP's ops vector for SWD mode. | |||
* messy - is there a better way? */ | |||
arm->dap->ops = &swd_dap_ops; | |||
/* First connect after init is not reconnecting. */ | |||
dap->do_reconnect = false; | |||
int retval = swd_connect(dap); | |||
if (retval != ERROR_OK) | |||
LOG_ERROR("SWD connect failed"); | |||
return retval; | |||
/* nothing done here, SWD is initialized | |||
* together with the DAP */ | |||
return ERROR_OK; | |||
} | |||
static struct transport swd_transport = { | |||
@@ -76,6 +76,7 @@ | |||
#include <helper/jep106.h> | |||
#include <helper/time_support.h> | |||
#include <helper/list.h> | |||
#include <helper/jim-nvp.h> | |||
/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ | |||
@@ -614,33 +615,8 @@ int mem_ap_write_buf_noincr(struct adiv5_ap *ap, | |||
#define DAP_POWER_DOMAIN_TIMEOUT (10) | |||
/* FIXME don't import ... just initialize as | |||
* part of DAP transport setup | |||
*/ | |||
extern const struct dap_ops jtag_dp_ops; | |||
/*--------------------------------------------------------------------------*/ | |||
/** | |||
* Create a new DAP | |||
*/ | |||
struct adiv5_dap *dap_init(void) | |||
{ | |||
struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap)); | |||
int i; | |||
/* Set up with safe defaults */ | |||
for (i = 0; i <= 255; i++) { | |||
dap->ap[i].dap = dap; | |||
dap->ap[i].ap_num = i; | |||
/* memaccess_tck max is 255 */ | |||
dap->ap[i].memaccess_tck = 255; | |||
/* Number of bits for tar autoincrement, impl. dep. at least 10 */ | |||
dap->ap[i].tar_autoincr_block = (1<<10); | |||
} | |||
INIT_LIST_HEAD(&dap->cmd_journal); | |||
return dap; | |||
} | |||
/** | |||
* Invalidate cached DP select and cached TAR and CSW of all APs | |||
*/ | |||
@@ -667,14 +643,7 @@ int dap_dp_init(struct adiv5_dap *dap) | |||
{ | |||
int retval; | |||
LOG_DEBUG(" "); | |||
/* JTAG-DP or SWJ-DP, in JTAG mode | |||
* ... for SWD mode this is patched as part | |||
* of link switchover | |||
* FIXME: This should already be setup by the respective transport specific DAP creation. | |||
*/ | |||
if (!dap->ops) | |||
dap->ops = &jtag_dp_ops; | |||
LOG_DEBUG("%s", adiv5_dap_name(dap)); | |||
dap_invalidate_cache(dap); | |||
@@ -1376,7 +1345,7 @@ static int dap_rom_display(struct command_context *cmd_ctx, | |||
return ERROR_OK; | |||
} | |||
static int dap_info_command(struct command_context *cmd_ctx, | |||
int dap_info_command(struct command_context *cmd_ctx, | |||
struct adiv5_ap *ap) | |||
{ | |||
int retval; | |||
@@ -1434,46 +1403,131 @@ static int dap_info_command(struct command_context *cmd_ctx, | |||
return ERROR_OK; | |||
} | |||
enum adiv5_cfg_param { | |||
CFG_DAP, | |||
CFG_AP_NUM | |||
}; | |||
static const Jim_Nvp nvp_config_opts[] = { | |||
{ .name = "-dap", .value = CFG_DAP }, | |||
{ .name = "-ap-num", .value = CFG_AP_NUM }, | |||
{ .name = NULL, .value = -1 } | |||
}; | |||
int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi) | |||
{ | |||
struct adiv5_private_config *pc; | |||
const char *arg; | |||
jim_wide ap_num; | |||
int e; | |||
/* check if argv[0] is for us */ | |||
arg = Jim_GetString(goi->argv[0], NULL); | |||
if (strcmp(arg, "-ap-num")) | |||
return JIM_CONTINUE; | |||
pc = (struct adiv5_private_config *)target->private_config; | |||
if (pc == NULL) { | |||
pc = calloc(1, sizeof(struct adiv5_private_config)); | |||
pc->ap_num = -1; | |||
target->private_config = pc; | |||
} | |||
e = Jim_GetOpt_String(goi, &arg, NULL); | |||
if (e != JIM_OK) | |||
return e; | |||
target->has_dap = true; | |||
if (goi->argc > 0) { | |||
Jim_Nvp *n; | |||
Jim_SetEmptyResult(goi->interp); | |||
/* check first if topmost item is for us */ | |||
e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts, | |||
goi->argv[0], &n); | |||
if (e != JIM_OK) | |||
return JIM_CONTINUE; | |||
e = Jim_GetOpt_Obj(goi, NULL); | |||
if (e != JIM_OK) | |||
return e; | |||
switch (n->value) { | |||
case CFG_DAP: | |||
if (goi->isconfigure) { | |||
Jim_Obj *o_t; | |||
struct adiv5_dap *dap; | |||
e = Jim_GetOpt_Obj(goi, &o_t); | |||
if (e != JIM_OK) | |||
return e; | |||
dap = dap_instance_by_jim_obj(goi->interp, o_t); | |||
if (dap == NULL) { | |||
Jim_SetResultString(goi->interp, "DAP name invalid!", -1); | |||
return JIM_ERR; | |||
} | |||
if (pc->dap != NULL && pc->dap != dap) { | |||
Jim_SetResultString(goi->interp, | |||
"DAP assignment cannot be changed after target was created!", -1); | |||
return JIM_ERR; | |||
} | |||
if (target->tap_configured) { | |||
Jim_SetResultString(goi->interp, | |||
"-chain-position and -dap configparams are mutually exclusive!", -1); | |||
return JIM_ERR; | |||
} | |||
pc->dap = dap; | |||
target->tap = dap->tap; | |||
target->dap_configured = true; | |||
} else { | |||
if (goi->argc != 0) { | |||
Jim_WrongNumArgs(goi->interp, | |||
goi->argc, goi->argv, | |||
"NO PARAMS"); | |||
return JIM_ERR; | |||
} | |||
if (pc->dap == NULL) { | |||
Jim_SetResultString(goi->interp, "DAP not configured", -1); | |||
return JIM_ERR; | |||
} | |||
Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1); | |||
} | |||
break; | |||
if (goi->argc == 0) { | |||
Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ..."); | |||
return JIM_ERR; | |||
case CFG_AP_NUM: | |||
if (goi->isconfigure) { | |||
jim_wide ap_num; | |||
e = Jim_GetOpt_Wide(goi, &ap_num); | |||
if (e != JIM_OK) | |||
return e; | |||
pc->ap_num = ap_num; | |||
} else { | |||
if (goi->argc != 0) { | |||
Jim_WrongNumArgs(goi->interp, | |||
goi->argc, goi->argv, | |||
"NO PARAMS"); | |||
return JIM_ERR; | |||
} | |||
if (pc->ap_num < 0) { | |||
Jim_SetResultString(goi->interp, "AP number not configured", -1); | |||
return JIM_ERR; | |||
} | |||
Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, (int)pc->ap_num)); | |||
} | |||
break; | |||
} | |||
} | |||
e = Jim_GetOpt_Wide(goi, &ap_num); | |||
if (e != JIM_OK) | |||
return e; | |||
return JIM_OK; | |||
} | |||
if (target->private_config == NULL) { | |||
pc = calloc(1, sizeof(struct adiv5_private_config)); | |||
target->private_config = pc; | |||
pc->ap_num = ap_num; | |||
} | |||
int adiv5_verify_config(struct adiv5_private_config *pc) | |||
{ | |||
if (pc == NULL) | |||
return ERROR_FAIL; | |||
if (pc->dap == NULL) | |||
return ERROR_FAIL; | |||
return JIM_OK; | |||
return ERROR_OK; | |||
} | |||
COMMAND_HANDLER(handle_dap_info_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t apsel; | |||
switch (CMD_ARGC) { | |||
@@ -1494,10 +1548,7 @@ COMMAND_HANDLER(handle_dap_info_command) | |||
COMMAND_HANDLER(dap_baseaddr_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t apsel, baseaddr; | |||
int retval; | |||
@@ -1534,10 +1585,7 @@ COMMAND_HANDLER(dap_baseaddr_command) | |||
COMMAND_HANDLER(dap_memaccess_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t memaccess_tck; | |||
switch (CMD_ARGC) { | |||
@@ -1560,10 +1608,7 @@ COMMAND_HANDLER(dap_memaccess_command) | |||
COMMAND_HANDLER(dap_apsel_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t apsel, apid; | |||
int retval; | |||
@@ -1598,11 +1643,9 @@ COMMAND_HANDLER(dap_apsel_command) | |||
COMMAND_HANDLER(dap_apcsw_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t apcsw = dap->ap[dap->apsel].csw_default; | |||
uint32_t sprot = 0; | |||
switch (CMD_ARGC) { | |||
case 0: | |||
@@ -1631,10 +1674,7 @@ COMMAND_HANDLER(dap_apcsw_command) | |||
COMMAND_HANDLER(dap_apid_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t apsel, apid; | |||
int retval; | |||
@@ -1666,10 +1706,7 @@ COMMAND_HANDLER(dap_apid_command) | |||
COMMAND_HANDLER(dap_apreg_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t apsel, reg, value; | |||
int retval; | |||
@@ -1705,10 +1742,7 @@ COMMAND_HANDLER(dap_apreg_command) | |||
COMMAND_HANDLER(dap_ti_be_32_quirks_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); | |||
uint32_t enable = dap->ti_be_32_quirks; | |||
switch (CMD_ARGC) { | |||
@@ -1729,7 +1763,7 @@ COMMAND_HANDLER(dap_ti_be_32_quirks_command) | |||
return 0; | |||
} | |||
static const struct command_registration dap_commands[] = { | |||
const struct command_registration dap_instance_commands[] = { | |||
{ | |||
.name = "info", | |||
.handler = handle_dap_info_command, | |||
@@ -1795,14 +1829,3 @@ static const struct command_registration dap_commands[] = { | |||
}, | |||
COMMAND_REGISTRATION_DONE | |||
}; | |||
const struct command_registration dap_command_handlers[] = { | |||
{ | |||
.name = "dap", | |||
.mode = COMMAND_EXEC, | |||
.help = "DAP command group", | |||
.usage = "", | |||
.chain = dap_commands, | |||
}, | |||
COMMAND_REGISTRATION_DONE | |||
}; |
@@ -254,6 +254,8 @@ struct adiv5_dap { | |||
* available until run(). | |||
*/ | |||
struct dap_ops { | |||
/** connect operation for SWD */ | |||
int (*connect)(struct adiv5_dap *dap); | |||
/** DP register read. */ | |||
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg, | |||
uint32_t *data); | |||
@@ -473,9 +475,6 @@ int mem_ap_read_buf_noincr(struct adiv5_ap *ap, | |||
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, | |||
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); | |||
/* Create DAP struct */ | |||
struct adiv5_dap *dap_init(void); | |||
/* Initialisation of the debug system, power domains and registers */ | |||
int dap_dp_init(struct adiv5_dap *dap); | |||
int mem_ap_init(struct adiv5_ap *ap); | |||
@@ -509,12 +508,24 @@ int dap_to_swd(struct target *target); | |||
/* Put debug link into JTAG mode */ | |||
int dap_to_jtag(struct target *target); | |||
extern const struct command_registration dap_command_handlers[]; | |||
extern const struct command_registration dap_instance_commands[]; | |||
struct arm_dap_object; | |||
extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o); | |||
extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj); | |||
extern int dap_info_command(struct command_context *cmd_ctx, | |||
struct adiv5_ap *ap); | |||
extern int dap_register_commands(struct command_context *cmd_ctx); | |||
extern const char *adiv5_dap_name(struct adiv5_dap *self); | |||
extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self); | |||
extern int dap_cleanup_all(void); | |||
struct adiv5_private_config { | |||
int ap_num; | |||
struct adiv5_dap *dap; | |||
}; | |||
extern int adiv5_verify_config(struct adiv5_private_config *pc); | |||
extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi); | |||
#endif /* OPENOCD_TARGET_ARM_ADI_V5_H */ |
@@ -365,22 +365,21 @@ static const struct command_registration cti_instance_command_handlers[] = { | |||
}; | |||
enum cti_cfg_param { | |||
CFG_CHAIN_POSITION, | |||
CFG_DAP, | |||
CFG_AP_NUM, | |||
CFG_CTIBASE | |||
}; | |||
static const Jim_Nvp nvp_config_opts[] = { | |||
{ .name = "-chain-position", .value = CFG_CHAIN_POSITION }, | |||
{ .name = "-ctibase", .value = CFG_CTIBASE }, | |||
{ .name = "-ap-num", .value = CFG_AP_NUM }, | |||
{ .name = "-dap", .value = CFG_DAP }, | |||
{ .name = "-ctibase", .value = CFG_CTIBASE }, | |||
{ .name = "-ap-num", .value = CFG_AP_NUM }, | |||
{ .name = NULL, .value = -1 } | |||
}; | |||
static int cti_configure(Jim_GetOptInfo *goi, struct arm_cti_object *cti) | |||
{ | |||
struct jtag_tap *tap = NULL; | |||
struct adiv5_dap *dap; | |||
struct adiv5_dap *dap = NULL; | |||
Jim_Nvp *n; | |||
jim_wide w; | |||
int e; | |||
@@ -395,14 +394,14 @@ static int cti_configure(Jim_GetOptInfo *goi, struct arm_cti_object *cti) | |||
return e; | |||
} | |||
switch (n->value) { | |||
case CFG_CHAIN_POSITION: { | |||
case CFG_DAP: { | |||
Jim_Obj *o_t; | |||
e = Jim_GetOpt_Obj(goi, &o_t); | |||
if (e != JIM_OK) | |||
return e; | |||
tap = jtag_tap_by_jim_obj(goi->interp, o_t); | |||
if (tap == NULL) { | |||
Jim_SetResultString(goi->interp, "-chain-position is invalid", -1); | |||
dap = dap_instance_by_jim_obj(goi->interp, o_t); | |||
if (dap == NULL) { | |||
Jim_SetResultString(goi->interp, "-dap is invalid", -1); | |||
return JIM_ERR; | |||
} | |||
/* loop for more */ | |||
@@ -424,18 +423,11 @@ static int cti_configure(Jim_GetOptInfo *goi, struct arm_cti_object *cti) | |||
} | |||
} | |||
if (tap == NULL) { | |||
Jim_SetResultString(goi->interp, "-chain-position required when creating CTI", -1); | |||
if (dap == NULL) { | |||
Jim_SetResultString(goi->interp, "-dap required when creating CTI", -1); | |||
return JIM_ERR; | |||
} | |||
if (tap->dap == NULL) { | |||
dap = dap_init(); | |||
dap->tap = tap; | |||
tap->dap = dap; | |||
} else | |||
dap = tap->dap; | |||
cti->cti.ap = dap_ap(dap, cti->ap_num); | |||
return JIM_OK; | |||
@@ -0,0 +1,366 @@ | |||
/*************************************************************************** | |||
* Copyright (C) 2016 by Matthias Welwarsky * | |||
* * | |||
* This program is free software; you can redistribute it and/or modify * | |||
* it under the terms of the GNU General Public License as published by * | |||
* the Free Software Foundation; either version 2 of the License, or * | |||
* (at your option) any later version. * | |||
* * | |||
* This program is distributed in the hope that it will be useful, * | |||
* but WITHOUT ANY WARRANTY; without even the implied warranty of * | |||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |||
* GNU General Public License for more details. * | |||
* * | |||
* You should have received a copy of the GNU General Public License * | |||
* along with this program; if not, write to the * | |||
* Free Software Foundation, Inc., * | |||
* * | |||
***************************************************************************/ | |||
#ifdef HAVE_CONFIG_H | |||
#include "config.h" | |||
#endif | |||
#include <stdlib.h> | |||
#include <stdint.h> | |||
#include "target/arm_adi_v5.h" | |||
#include "target/arm.h" | |||
#include "helper/list.h" | |||
#include "helper/command.h" | |||
#include "transport/transport.h" | |||
#include "jtag/interface.h" | |||
static LIST_HEAD(all_dap); | |||
extern const struct dap_ops swd_dap_ops; | |||
extern const struct dap_ops jtag_dp_ops; | |||
extern struct jtag_interface *jtag_interface; | |||
/* DAP command support */ | |||
struct arm_dap_object { | |||
struct list_head lh; | |||
struct adiv5_dap dap; | |||
char *name; | |||
const struct swd_driver *swd; | |||
}; | |||
static void dap_instance_init(struct adiv5_dap *dap) | |||
{ | |||
int i; | |||
/* Set up with safe defaults */ | |||
for (i = 0; i <= 255; i++) { | |||
dap->ap[i].dap = dap; | |||
dap->ap[i].ap_num = i; | |||
/* memaccess_tck max is 255 */ | |||
dap->ap[i].memaccess_tck = 255; | |||
/* Number of bits for tar autoincrement, impl. dep. at least 10 */ | |||
dap->ap[i].tar_autoincr_block = (1<<10); | |||
} | |||
INIT_LIST_HEAD(&dap->cmd_journal); | |||
} | |||
const char *adiv5_dap_name(struct adiv5_dap *self) | |||
{ | |||
struct arm_dap_object *obj = container_of(self, struct arm_dap_object, dap); | |||
return obj->name; | |||
} | |||
const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self) | |||
{ | |||
struct arm_dap_object *obj = container_of(self, struct arm_dap_object, dap); | |||
return obj->swd; | |||
} | |||
struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj) | |||
{ | |||
return &obj->dap; | |||
} | |||
struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o) | |||
{ | |||
struct arm_dap_object *obj = NULL; | |||
const char *name; | |||
bool found = false; | |||
name = Jim_GetString(o, NULL); | |||
list_for_each_entry(obj, &all_dap, lh) { | |||
if (!strcmp(name, obj->name)) { | |||
found = true; | |||
break; | |||
} | |||
} | |||
if (found) | |||
return &obj->dap; | |||
return NULL; | |||
} | |||
static int dap_init_all(void) | |||
{ | |||
struct arm_dap_object *obj; | |||
int retval; | |||
LOG_DEBUG("Initializing all DAPs ..."); | |||
list_for_each_entry(obj, &all_dap, lh) { | |||
struct adiv5_dap *dap = &obj->dap; | |||
/* with hla, dap is just a dummy */ | |||
if (transport_is_hla()) | |||
continue; | |||
/* skip taps that are disabled */ | |||
if (!dap->tap->enabled) | |||
continue; | |||
if (transport_is_swd()) { | |||
dap->ops = &swd_dap_ops; | |||
obj->swd = jtag_interface->swd; | |||
} else | |||
dap->ops = &jtag_dp_ops; | |||
retval = dap->ops->connect(dap); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
} | |||
return ERROR_OK; | |||
} | |||
int dap_cleanup_all(void) | |||
{ | |||
struct arm_dap_object *obj, *tmp; | |||
list_for_each_entry_safe(obj, tmp, &all_dap, lh) { | |||
free(obj->name); | |||
free(obj); | |||
} | |||
return ERROR_OK; | |||
} | |||
enum dap_cfg_param { | |||
CFG_CHAIN_POSITION, | |||
}; | |||
static const Jim_Nvp nvp_config_opts[] = { | |||
{ .name = "-chain-position", .value = CFG_CHAIN_POSITION }, | |||
{ .name = NULL, .value = -1 } | |||
}; | |||
static int dap_configure(Jim_GetOptInfo *goi, struct arm_dap_object *dap) | |||
{ | |||
struct jtag_tap *tap = NULL; | |||
Jim_Nvp *n; | |||
int e; | |||
/* parse config or cget options ... */ | |||
while (goi->argc > 0) { | |||
Jim_SetEmptyResult(goi->interp); | |||
e = Jim_GetOpt_Nvp(goi, nvp_config_opts, &n); | |||
if (e != JIM_OK) { | |||
Jim_GetOpt_NvpUnknown(goi, nvp_config_opts, 0); | |||
return e; | |||
} | |||
switch (n->value) { | |||
case CFG_CHAIN_POSITION: { | |||
Jim_Obj *o_t; | |||
e = Jim_GetOpt_Obj(goi, &o_t); | |||
if (e != JIM_OK) | |||
return e; | |||
tap = jtag_tap_by_jim_obj(goi->interp, o_t); | |||
if (tap == NULL) { | |||
Jim_SetResultString(goi->interp, "-chain-position is invalid", -1); | |||
return JIM_ERR; | |||
} | |||
/* loop for more */ | |||
break; | |||
} | |||
default: | |||
break; | |||
} | |||
} | |||
if (tap == NULL) { | |||
Jim_SetResultString(goi->interp, "-chain-position required when creating DAP", -1); | |||
return JIM_ERR; | |||
} | |||
dap_instance_init(&dap->dap); | |||
dap->dap.tap = tap; | |||
return JIM_OK; | |||
} | |||
static int dap_create(Jim_GetOptInfo *goi) | |||
{ | |||
struct command_context *cmd_ctx; | |||
static struct arm_dap_object *dap; | |||
Jim_Obj *new_cmd; | |||
Jim_Cmd *cmd; | |||
const char *cp; | |||
int e; | |||
cmd_ctx = current_command_context(goi->interp); | |||
assert(cmd_ctx != NULL); | |||
if (goi->argc < 3) { | |||
Jim_WrongNumArgs(goi->interp, 1, goi->argv, "?name? ..options..."); | |||
return JIM_ERR; | |||
} | |||
/* COMMAND */ | |||
Jim_GetOpt_Obj(goi, &new_cmd); | |||
/* does this command exist? */ | |||
cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_ERRMSG); | |||
if (cmd) { | |||
cp = Jim_GetString(new_cmd, NULL); | |||
Jim_SetResultFormatted(goi->interp, "Command: %s Exists", cp); | |||
return JIM_ERR; | |||
} | |||
/* Create it */ | |||
dap = calloc(1, sizeof(struct arm_dap_object)); | |||
if (dap == NULL) | |||
return JIM_ERR; | |||
e = dap_configure(goi, dap); | |||
if (e != JIM_OK) { | |||
free(dap); | |||
return e; | |||
} | |||
cp = Jim_GetString(new_cmd, NULL); | |||
dap->name = strdup(cp); | |||
struct command_registration dap_commands[] = { | |||
{ | |||
.name = cp, | |||
.mode = COMMAND_ANY, | |||
.help = "dap instance command group", | |||
.usage = "", | |||
.chain = dap_instance_commands, | |||
}, | |||
COMMAND_REGISTRATION_DONE | |||
}; | |||
/* don't expose the instance commands when using hla */ | |||
if (transport_is_hla()) | |||
dap_commands[0].chain = NULL; | |||
e = register_commands(cmd_ctx, NULL, dap_commands); | |||
if (ERROR_OK != e) | |||
return JIM_ERR; | |||
struct command *c = command_find_in_context(cmd_ctx, cp); | |||
assert(c); | |||
command_set_handler_data(c, dap); | |||
list_add_tail(&dap->lh, &all_dap); | |||
return (ERROR_OK == e) ? JIM_OK : JIM_ERR; | |||
} | |||
static int jim_dap_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) | |||
{ | |||
Jim_GetOptInfo goi; | |||
Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); | |||
if (goi.argc < 2) { | |||
Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, | |||
"<name> [<dap_options> ...]"); | |||
return JIM_ERR; | |||
} | |||
return dap_create(&goi); | |||
} | |||
static int jim_dap_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) | |||
{ | |||
struct arm_dap_object *obj; | |||
if (argc != 1) { | |||
Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); | |||
return JIM_ERR; | |||
} | |||
Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); | |||
list_for_each_entry(obj, &all_dap, lh) { | |||
Jim_ListAppendElement(interp, Jim_GetResult(interp), | |||
Jim_NewStringObj(interp, obj->name, -1)); | |||
} | |||
return JIM_OK; | |||
} | |||
COMMAND_HANDLER(handle_dap_init) | |||
{ | |||
return dap_init_all(); | |||
} | |||
COMMAND_HANDLER(handle_dap_info_command) | |||
{ | |||
struct target *target = get_current_target(CMD_CTX); | |||
struct arm *arm = target_to_arm(target); | |||
struct adiv5_dap *dap = arm->dap; | |||
uint32_t apsel; | |||
switch (CMD_ARGC) { | |||
case 0: | |||
apsel = dap->apsel; | |||
break; | |||
case 1: | |||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); | |||
if (apsel >= 256) | |||
return ERROR_COMMAND_SYNTAX_ERROR; | |||
break; | |||
default: | |||
return ERROR_COMMAND_SYNTAX_ERROR; | |||
} | |||
return dap_info_command(CMD_CTX, &dap->ap[apsel]); | |||
} | |||
static const struct command_registration dap_subcommand_handlers[] = { | |||
{ | |||
.name = "create", | |||
.mode = COMMAND_ANY, | |||
.jim_handler = jim_dap_create, | |||
.usage = "name '-chain-position' name", | |||
.help = "Creates a new DAP instance", | |||
}, | |||
{ | |||
.name = "names", | |||
.mode = COMMAND_ANY, | |||
.jim_handler = jim_dap_names, | |||
.usage = "", | |||
.help = "Lists all registered DAP instances by name", | |||
}, | |||
{ | |||
.name = "init", | |||
.mode = COMMAND_ANY, | |||
.handler = handle_dap_init, | |||
.usage = "", | |||
.help = "Initialize all registered DAP instances" | |||
}, | |||
{ | |||
.name = "info", | |||
.handler = handle_dap_info_command, | |||
.mode = COMMAND_EXEC, | |||
.help = "display ROM table for MEM-AP of current target " | |||
"(default currently selected AP)", | |||
.usage = "[ap_num]", | |||
}, | |||
COMMAND_REGISTRATION_DONE | |||
}; | |||
static const struct command_registration dap_commands[] = { | |||
{ | |||
.name = "dap", | |||
.mode = COMMAND_CONFIG, | |||
.help = "DAP commands", | |||
.chain = dap_subcommand_handlers, | |||
}, | |||
COMMAND_REGISTRATION_DONE | |||
}; | |||
int dap_register_commands(struct command_context *cmd_ctx) | |||
{ | |||
return register_commands(cmd_ctx, NULL, dap_commands); | |||
} |
@@ -776,9 +776,6 @@ const struct command_registration l2x_cache_command_handlers[] = { | |||
}; | |||
const struct command_registration armv7a_command_handlers[] = { | |||
{ | |||
.chain = dap_command_handlers, | |||
}, | |||
{ | |||
.chain = l2x_cache_command_handlers, | |||
}, | |||
@@ -843,8 +843,5 @@ const struct command_registration armv7m_command_handlers[] = { | |||
{ | |||
.chain = arm_command_handlers, | |||
}, | |||
{ | |||
.chain = dap_command_handlers, | |||
}, | |||
COMMAND_REGISTRATION_DONE | |||
}; |
@@ -1609,13 +1609,9 @@ struct reg *armv8_reg_current(struct arm *arm, unsigned regnum) | |||
} | |||
const struct command_registration armv8_command_handlers[] = { | |||
{ | |||
.chain = dap_command_handlers, | |||
}, | |||
COMMAND_REGISTRATION_DONE | |||
}; | |||
int armv8_get_gdb_reg_list(struct target *target, | |||
struct reg **reg_list[], int *reg_list_size, | |||
enum target_register_class reg_class) | |||
@@ -2947,12 +2947,6 @@ static int cortex_a_examine_first(struct target *target) | |||
int retval = ERROR_OK; | |||
uint32_t didr, cpuid, dbg_osreg; | |||
retval = dap_dp_init(swjdp); | |||
if (retval != ERROR_OK) { | |||
LOG_ERROR("Could not initialize the debug port"); | |||
return retval; | |||
} | |||
/* Search for the APB-AP - it is needed for access to debug registers */ | |||
retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap); | |||
if (retval != ERROR_OK) { | |||
@@ -3134,22 +3128,13 @@ static int cortex_a_init_target(struct command_context *cmd_ctx, | |||
} | |||
static int cortex_a_init_arch_info(struct target *target, | |||
struct cortex_a_common *cortex_a, struct jtag_tap *tap) | |||
struct cortex_a_common *cortex_a, struct adiv5_dap *dap) | |||
{ | |||
struct armv7a_common *armv7a = &cortex_a->armv7a_common; | |||
/* Setup struct cortex_a_common */ | |||
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC; | |||
/* tap has no dap initialized */ | |||
if (!tap->dap) { | |||
tap->dap = dap_init(); | |||
/* Leave (only) generic DAP stuff for debugport_init() */ | |||
tap->dap->tap = tap; | |||
} | |||
armv7a->arm.dap = tap->dap; | |||
armv7a->arm.dap = dap; | |||
cortex_a->fast_reg_read = 0; | |||
@@ -3175,21 +3160,34 @@ static int cortex_a_init_arch_info(struct target *target, | |||
static int cortex_a_target_create(struct target *target, Jim_Interp *interp) | |||
{ | |||
struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common)); | |||
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC; | |||
struct adiv5_private_config *pc; | |||
if (target->private_config == NULL) | |||
return ERROR_FAIL; | |||
pc = (struct adiv5_private_config *)target->private_config; | |||
cortex_a->armv7a_common.is_armv7r = false; | |||
cortex_a->armv7a_common.arm.arm_vfp_version = ARM_VFP_V3; | |||
return cortex_a_init_arch_info(target, cortex_a, target->tap); | |||
return cortex_a_init_arch_info(target, cortex_a, pc->dap); | |||
} | |||
static int cortex_r4_target_create(struct target *target, Jim_Interp *interp) | |||
{ | |||
struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common)); | |||
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC; | |||
struct adiv5_private_config *pc; | |||
pc = (struct adiv5_private_config *)target->private_config; | |||
if (adiv5_verify_config(pc) != ERROR_OK) | |||
return ERROR_FAIL; | |||
cortex_a->armv7a_common.is_armv7r = true; | |||
return cortex_a_init_arch_info(target, cortex_a, target->tap); | |||
return cortex_a_init_arch_info(target, cortex_a, pc->dap); | |||
} | |||
static void cortex_a_deinit_target(struct target *target) | |||
@@ -3200,6 +3198,7 @@ static void cortex_a_deinit_target(struct target *target) | |||
free(cortex_a->brp_list); | |||
free(dpm->dbp); | |||
free(dpm->dwp); | |||
free(target->private_config); | |||
free(cortex_a); | |||
} | |||
@@ -3484,6 +3483,7 @@ struct target_type cortexa_target = { | |||
.commands = cortex_a_command_handlers, | |||
.target_create = cortex_a_target_create, | |||
.target_jim_configure = adiv5_jim_configure, | |||
.init_target = cortex_a_init_target, | |||
.examine = cortex_a_examine, | |||
.deinit_target = cortex_a_deinit_target, | |||
@@ -3516,9 +3516,6 @@ static const struct command_registration cortex_r4_command_handlers[] = { | |||
{ | |||
.chain = arm_command_handlers, | |||
}, | |||
{ | |||
.chain = dap_command_handlers, | |||
}, | |||
{ | |||
.name = "cortex_r4", | |||
.mode = COMMAND_ANY, | |||
@@ -3562,6 +3559,7 @@ struct target_type cortexr4_target = { | |||
.commands = cortex_r4_command_handlers, | |||
.target_create = cortex_r4_target_create, | |||
.target_jim_configure = adiv5_jim_configure, | |||
.init_target = cortex_a_init_target, | |||
.examine = cortex_a_examine, | |||
.deinit_target = cortex_a_deinit_target, | |||
@@ -1992,12 +1992,6 @@ int cortex_m_examine(struct target *target) | |||
/* stlink shares the examine handler but does not support | |||
* all its calls */ | |||
if (!armv7m->stlink) { | |||
retval = dap_dp_init(swjdp); | |||
if (retval != ERROR_OK) { | |||
LOG_ERROR("Could not initialize the debug port"); | |||
return retval; | |||
} | |||
if (cortex_m->apsel < 0) { | |||
/* Search for the MEM-AP */ | |||
retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap); | |||
@@ -2228,25 +2222,17 @@ static int cortex_m_handle_target_request(void *priv) | |||
} | |||
static int cortex_m_init_arch_info(struct target *target, | |||
struct cortex_m_common *cortex_m, struct jtag_tap *tap) | |||
struct cortex_m_common *cortex_m, struct adiv5_dap *dap) | |||
{ | |||
struct armv7m_common *armv7m = &cortex_m->armv7m; | |||
armv7m_init_arch_info(target, armv7m); | |||
/* tap has no dap initialized */ | |||
if (!tap->dap) { | |||
tap->dap = dap_init(); | |||
/* Leave (only) generic DAP stuff for debugport_init() */ | |||
tap->dap->tap = tap; | |||
} | |||
/* default reset mode is to use srst if fitted | |||
* if not it will use CORTEX_M3_RESET_VECTRESET */ | |||
cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET; | |||
armv7m->arm.dap = tap->dap; | |||
armv7m->arm.dap = dap; | |||
/* register arch-specific functions */ | |||
armv7m->examine_debug_reason = cortex_m_examine_debug_reason; | |||
@@ -2266,16 +2252,16 @@ static int cortex_m_init_arch_info(struct target *target, | |||
static int cortex_m_target_create(struct target *target, Jim_Interp *interp) | |||
{ | |||
struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common)); | |||
cortex_m->common_magic = CORTEX_M_COMMON_MAGIC; | |||
cortex_m_init_arch_info(target, cortex_m, target->tap); | |||
if (target->private_config != NULL) { | |||
struct adiv5_private_config *pc = | |||
(struct adiv5_private_config *)target->private_config; | |||
cortex_m->apsel = pc->ap_num; | |||
} else | |||
cortex_m->apsel = -1; | |||
struct adiv5_private_config *pc; | |||
pc = (struct adiv5_private_config *)target->private_config; | |||
if (adiv5_verify_config(pc) != ERROR_OK) | |||
return ERROR_FAIL; | |||
cortex_m->apsel = pc->ap_num; | |||
cortex_m_init_arch_info(target, cortex_m, pc->dap); | |||
return ERROR_OK; | |||
} | |||
@@ -365,12 +365,16 @@ static int adapter_target_create(struct target *target, | |||
Jim_Interp *interp) | |||
{ | |||
LOG_DEBUG("%s", __func__); | |||
struct adiv5_private_config *pc = target->private_config; | |||
struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common)); | |||
if (!cortex_m) | |||
return ERROR_COMMAND_SYNTAX_ERROR; | |||
if (pc != NULL && pc->ap_num > 0) { | |||
LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)"); | |||
return ERROR_FAIL; | |||
} | |||
adapter_init_arch_info(target, cortex_m, target->tap); | |||
return ERROR_OK; | |||
@@ -801,6 +805,7 @@ struct target_type hla_target = { | |||
.init_target = adapter_init_target, | |||
.deinit_target = cortex_m_deinit_target, | |||
.target_create = adapter_target_create, | |||
.target_jim_configure = adiv5_jim_configure, | |||
.examine = cortex_m_examine, | |||
.commands = adapter_command_handlers, | |||
@@ -4765,6 +4765,13 @@ no_params: | |||
if (goi->isconfigure) { | |||
Jim_Obj *o_t; | |||
struct jtag_tap *tap; | |||
if (target->has_dap) { | |||
Jim_SetResultString(goi->interp, | |||
"target requires -dap parameter instead of -chain-position!", -1); | |||
return JIM_ERR; | |||
} | |||
target_free_all_working_areas(target); | |||
e = Jim_GetOpt_Obj(goi, &o_t); | |||
if (e != JIM_OK) | |||
@@ -4772,8 +4779,8 @@ no_params: | |||
tap = jtag_tap_by_jim_obj(goi->interp, o_t); | |||
if (tap == NULL) | |||
return JIM_ERR; | |||
/* make this exactly 1 or 0 */ | |||
target->tap = tap; | |||
target->tap_configured = true; | |||
} else { | |||
if (goi->argc != 0) | |||
goto no_params; | |||
@@ -5591,9 +5598,21 @@ static int target_create(Jim_GetOptInfo *goi) | |||
goi->isconfigure = 1; | |||
e = target_configure(goi, target); | |||
if (target->tap == NULL) { | |||
Jim_SetResultString(goi->interp, "-chain-position required when creating target", -1); | |||
e = JIM_ERR; | |||
if (e == JIM_OK) { | |||
if (target->has_dap) { | |||
if (!target->dap_configured) { | |||
Jim_SetResultString(goi->interp, "-dap ?name? required when creating target", -1); | |||
e = JIM_ERR; | |||
} | |||
} else { | |||
if (!target->tap_configured) { | |||
Jim_SetResultString(goi->interp, "-chain-position ?name? required when creating target", -1); | |||
e = JIM_ERR; | |||
} | |||
} | |||
/* tap must be set after target was configured */ | |||
if (target->tap == NULL) | |||
e = JIM_ERR; | |||
} | |||
if (e != JIM_OK) { | |||
@@ -5610,14 +5629,23 @@ static int target_create(Jim_GetOptInfo *goi) | |||
cp = Jim_GetString(new_cmd, NULL); | |||
target->cmd_name = strdup(cp); | |||
if (target->type->target_create) { | |||
e = (*(target->type->target_create))(target, goi->interp); | |||
if (e != ERROR_OK) { | |||
LOG_DEBUG("target_create failed"); | |||
free(target->type); | |||
free(target->cmd_name); | |||
free(target); | |||
return JIM_ERR; | |||
} | |||
} | |||
/* create the target specific commands */ | |||
if (target->type->commands) { | |||
e = register_commands(cmd_ctx, NULL, target->type->commands); | |||
if (ERROR_OK != e) | |||
LOG_ERROR("unable to register '%s' commands", cp); | |||
} | |||
if (target->type->target_create) | |||
(*(target->type->target_create))(target, goi->interp); | |||
/* append to end of list */ | |||
{ | |||
@@ -181,10 +181,15 @@ struct target { | |||
bool halt_issued; /* did we transition to halted state? */ | |||
int64_t halt_issued_time; /* Note time when halt was issued */ | |||
/* ARM v7/v8 targets with ADIv5 interface */ | |||
bool dbgbase_set; /* By default the debug base is not set */ | |||
uint32_t dbgbase; /* Really a Cortex-A specific option, but there is no | |||
* system in place to support target specific options | |||
* currently. */ | |||
bool has_dap; /* set to true if target has ADIv5 support */ | |||
bool dap_configured; /* set to true if ADIv5 DAP is configured */ | |||
bool tap_configured; /* set to true if JTAG tap has been configured | |||
* through -chain-position */ | |||
struct rtos *rtos; /* Instance of Real Time Operating System support */ | |||
bool rtos_auto_detect; /* A flag that indicates that the RTOS has been specified as "auto" | |||
@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
# use AHB-Lite SRAM for work area | |||
$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -27,9 +27,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -event examine-end { | |||
global _TARGETNAME | |||
@@ -32,7 +32,8 @@ if { [info exists CPUTAPID] } { | |||
set _CPUTAPID 0x2ba01477 | |||
} | |||
swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
# SWD/JTAG speed | |||
adapter_khz 1000 | |||
@@ -41,7 +42,7 @@ adapter_khz 1000 | |||
## Target configuration | |||
## | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
# allocate the working area | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -14,7 +14,7 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x4ba00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ | |||
-expected-id $_DAP_TAPID | |||
# Subsidiary TAP: fpga | |||
@@ -42,7 +42,8 @@ set _TARGETNAME1 $_CHIPNAME.cpu.0 | |||
set _TARGETNAME2 $_CHIPNAME.cpu.1 | |||
# A9 core 0 | |||
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \ | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 0 -dbgbase 0x80110000 | |||
$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 } | |||
@@ -51,7 +52,7 @@ $_TARGETNAME1 configure -event gdb-attach { halt } | |||
# A9 core 1 | |||
#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \ | |||
#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \ | |||
# -coreid 1 -dbgbase 0x80112000 | |||
#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 } | |||
@@ -12,7 +12,7 @@ if { [info exists CHIPNAME] } { | |||
if { [info exists DEFAULT_TAPS] } { | |||
set _DEFAULT_TAPS "$DEFAULT_TAPS" | |||
} else { | |||
set _DEFAULT_TAPS "$_CHIPNAME.dap" | |||
set _DEFAULT_TAPS "$_CHIPNAME.tap" | |||
} | |||
# | |||
@@ -23,8 +23,9 @@ if { [info exists DAP_TAPID] } { | |||
} else { | |||
set _DAP_TAPID 0x4b6b902f | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0" | |||
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0" | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap | |||
# | |||
# M3 DAP | |||
@@ -34,8 +35,9 @@ if { [info exists M3_DAP_TAPID] } { | |||
} else { | |||
set _M3_DAP_TAPID 0x4b6b902f | |||
} | |||
jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0" | |||
jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0" | |||
dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap | |||
# | |||
# ICEpick-D (JTAG route controller) | |||
@@ -66,13 +68,13 @@ proc enable_default_taps { taps } { | |||
# Cortex-M3 target | |||
# | |||
set _TARGETNAME_2 $_CHIPNAME.m3 | |||
target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap | |||
target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap | |||
# | |||
# Cortex-A8 target | |||
# | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000 | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000 | |||
# SRAM: 64K at 0x4030.0000; use the first 16K | |||
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000 | |||
@@ -458,6 +458,7 @@ if { [info exists M3_DAP_TAPID] } { | |||
} | |||
jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable | |||
jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0" | |||
dap create $M3_NAME.dap -chain-position $M3_NAME | |||
# | |||
# DebugSS DAP | |||
@@ -469,6 +470,7 @@ if { [info exists DAP_TAPID] } { | |||
} | |||
jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable | |||
jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0" | |||
dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME | |||
# | |||
# ICEpick-D (JTAG route controller) | |||
@@ -486,7 +488,7 @@ jtag configure $JRC_NAME -event post-reset "runtest 100" | |||
# | |||
# Cortex-A9 target | |||
# | |||
target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000 | |||
target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000 | |||
# SRAM: 256K at 0x4030.0000 | |||
@@ -86,8 +86,8 @@ source [find target/icepick.cfg] | |||
# Secondary TAP: DAP is closest to the TDO output | |||
# The TAP enable event also needs to be described | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable | |||
jtag configure $_CHIPNAME.cpu -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 3" | |||
# These taps are only present in the DM37x series. | |||
@@ -141,7 +141,8 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" | |||
# Create the CPU target to be used with GDB: Cortex-A8, using DAP | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap | |||
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first | |||
# 16K to be used as a scratchpad for OpenOCD. | |||
@@ -16,10 +16,11 @@ if { [info exists CPUTAPID] } { | |||
set _CPUTAPID 0x4ba00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap | |||
proc armada370_dbginit {target} { | |||
cortex_a dbginit | |||
@@ -55,9 +55,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
# 16K is plenty, the smallest chip has this much | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -18,9 +18,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap | |||
set _FLASHNAME $_CHIPNAME.flash | |||
flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME | |||
@@ -35,9 +35,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
# 16K is plenty, the smallest chip has this much | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -32,9 +32,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -14,15 +14,17 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x4ba00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4 | |||
jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4 | |||
# Dual Cortex-A9 | |||
set _TARGETNAME0 $_CHIPNAME.cpu0 | |||
set _TARGETNAME1 $_CHIPNAME.cpu1 | |||
target create $_TARGETNAME0 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000 | |||
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000 | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000 | |||
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000 | |||
target smp $_TARGETNAME0 $_TARGETNAME1 | |||
$_TARGETNAME0 configure -event gdb-attach { | |||
@@ -29,12 +29,13 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
set WDOG_VALUE 0 | |||
set WDOG_VALUE_SET 0 | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -19,8 +19,8 @@ if { [info exists DAP_TAPID] } { | |||
} else { | |||
set _DAP_TAPID 0x4BA00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" | |||
# | |||
# ICEpick-C (JTAG route controller) | |||
@@ -33,11 +33,12 @@ if { [info exists JRC_TAPID] } { | |||
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version | |||
# A start sequence is needed to change from cJTAG (Compact JTAG) to | |||
# 4-pin JTAG before talking via JTAG commands | |||
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" | |||
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" | |||
jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc" | |||
# | |||
# Cortex-M3 target | |||
# | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap |
@@ -26,10 +26,10 @@ if { [info exists DAP_TAPID] } { | |||
} | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" | |||
} else { | |||
swj_newdap $_CHIPNAME dap -expected-id $_DAP_TAPID | |||
swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID | |||
} | |||
# | |||
@@ -50,4 +50,5 @@ if {[using_jtag]} { | |||
# Cortex-M3 target | |||
# | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap |
@@ -32,11 +32,12 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
adapter_khz 1000 | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -50,12 +50,13 @@ if { [info exists FLASHSIZE] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if { [using_jtag] } { | |||
swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -17,7 +17,8 @@ if { [info exists CPUTAPID] } { | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create ${_TARGETNAME}0 cortex_a -chain-position $_TARGETNAME | |||
target create ${_TARGETNAME}1 cortex_a -chain-position $_TARGETNAME | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap | |||
target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap | |||
target smp ${_TARGETNAME}0 ${_TARGETNAME}1 |
@@ -31,9 +31,10 @@ if {[using_jtag]} { | |||
reset_config trst_only | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
# MB9BF506 has 64kB of SRAM on its main system bus | |||
$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0 | |||
@@ -19,9 +19,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap | |||
adapter_khz 500 | |||
@@ -16,8 +16,8 @@ if { [info exists DAP_TAPID] } { | |||
} | |||
# declare the one JTAG tap to access the DAP | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
# declare the 4 main application cores | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
set _smp_command "" | |||
@@ -33,7 +33,7 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } { | |||
cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0 | |||
set _command "target create ${_TARGETNAME}$_core aarch64 \ | |||
-chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]" | |||
-dap $_CHIPNAME.dap -coreid $_core -cti cti$_core" | |||
if { $_core != 0 } { | |||
# non-boot core examination may fail | |||
@@ -16,7 +16,10 @@ if { [info exists DAP_TAPID] } { | |||
} | |||
# declare the one JTAG tap to access the DAP | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable | |||
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version | |||
# create the DAP | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap | |||
# declare the 8 main application cores | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
@@ -34,10 +37,10 @@ set $_TARGETNAME.cti(7) 0x801DB000 | |||
set _cores 8 | |||
for { set _core 0 } { $_core < $_cores } { incr _core 1 } { | |||
cti create cti$_core -chain-position $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0 | |||
cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0 | |||
set _command "target create ${_TARGETNAME}$_core aarch64 \ | |||
-chain-position $_CHIPNAME.dap -coreid $_core -cti cti$_core" | |||
-dap $_CHIPNAME.dap -coreid $_core -cti cti$_core" | |||
if { $_core != 0 } { | |||
# non-boot core examination may fail | |||
@@ -54,10 +57,10 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } { | |||
eval $_smp_command | |||
cti create cti.sys -chain-position hi6220.dap -ap-num 0 -ctibase 0x80003000 | |||
cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0x80003000 | |||
# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin) | |||
target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 2 -defer-examine | |||
target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine | |||
# declare the auxiliary Cortex-A7 core | |||
target create ${_TARGETNAME}.a7 cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine | |||
target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine |
@@ -13,11 +13,11 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x1ba00477 | |||
} | |||
jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_DAP_TAPID | |||
# SDMA / no IDCODE | |||
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf | |||
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf | |||
# SJC | |||
if { [info exists SJC_TAPID] } { | |||
@@ -26,15 +26,16 @@ if { [info exists SJC_TAPID] } { | |||
set _SJC_TAPID 0x0190c01d | |||
} | |||
jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ | |||
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \ | |||
-expected-id $_SJC_TAPID -ignore-version | |||
# GDB target: Cortex-A8, using DAP | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap | |||
# some TCK tycles are required to activate the DEBUG power domain | |||
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" | |||
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" | |||
proc imx51_dbginit {target} { | |||
# General Cortex-A8 debug initialisation | |||
@@ -13,11 +13,11 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x1ba00477 | |||
} | |||
jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_DAP_TAPID | |||
# SDMA / no IDCODE | |||
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf | |||
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf | |||
# SJC | |||
if { [info exists SJC_TAPID] } { | |||
@@ -26,15 +26,16 @@ if { [info exists SJC_TAPID] } { | |||
set _SJC_TAPID 0x0190d01d | |||
} | |||
jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ | |||
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \ | |||
-expected-id $_SJC_TAPID -ignore-version | |||
# GDB target: Cortex-A8, using DAP | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap | |||
# some TCK tycles are required to activate the DEBUG power domain | |||
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100" | |||
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" | |||
proc imx53_dbginit {target} { | |||
# General Cortex-A8 debug initialisation | |||
@@ -13,7 +13,7 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x4ba00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ | |||
-expected-id $_DAP_TAPID | |||
# SDMA / no IDCODE | |||
@@ -40,7 +40,8 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ | |||
# core 2 - 0x82154000 | |||
# core 3 - 0x82156000 | |||
set _TARGETNAME $_CHIPNAME.cpu.0 | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 0 -dbgbase 0x82150000 | |||
# some TCK cycles are required to activate the DEBUG power domain | |||
@@ -11,7 +11,7 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x5ba00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ | |||
-expected-id $_DAP_TAPID | |||
# | |||
@@ -22,16 +22,19 @@ jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ | |||
# core 0 - 0x80070000 | |||
# core 1 - 0x80072000 | |||
set _TARGETNAME $_CHIPNAME.cpu_a7 | |||
target create $_TARGETNAME.0 cortex_a -chain-position $_CHIPNAME.dap \ | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 0 -dbgbase 0x80070000 | |||
target create $_TARGETNAME.1 cortex_a -chain-position $_CHIPNAME.dap \ | |||
target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 1 -dbgbase 0x80072000 -defer-examine | |||
# | |||
# Cortex-M4 target | |||
# | |||
set _TARGETNAME_2 $_CHIPNAME.cpu_m4 | |||
target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.dap -ap-num 4 \ | |||
target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \ | |||
-defer-examine | |||
targets $_TARGETNAME.0 |
@@ -31,9 +31,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -25,9 +25,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -26,9 +26,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -30,9 +30,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -23,9 +23,10 @@ if { [info exists M3_JTAG_TAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3 | |||
set _TARGETNAME $_CHIPNAME.m3 | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
if {![using_hla]} { | |||
# if srst is not fitted use SYSRESETREQ to | |||
@@ -75,9 +75,10 @@ if { [info exists WORKAREASIZE] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) | |||
# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) | |||
@@ -43,12 +43,14 @@ if { [info exists M0_JTAG_TAPID] } { | |||
swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M4_TAPID | |||
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 | |||
dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4 | |||
target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap | |||
if { [using_jtag] } { | |||
swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M0_JTAG_TAPID | |||
target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 | |||
dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0 | |||
target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap | |||
} | |||
# LPC4350 has 96+32 KB SRAM | |||
@@ -47,8 +47,8 @@ if { [info exists M0_JTAG_TAPID] } { | |||
swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M4_TAPID | |||
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 | |||
dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4 | |||
target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap | |||
# LPC4370 has 96+32 KB contiguous SRAM | |||
if { [info exists WORKAREASIZE] } { | |||
@@ -65,8 +65,10 @@ if { [using_jtag] } { | |||
jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M0_JTAG_TAPID | |||
target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app | |||
target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub | |||
dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app | |||
dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub | |||
target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap | |||
target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap | |||
# 32+8+32 KB SRAM | |||
$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \ | |||
@@ -35,7 +35,8 @@ if { [info exists DAP_TAPID] } { | |||
} | |||
# declare the one JTAG tap to access the DAP | |||
swj_newdap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
# declare the main application cores | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
@@ -43,10 +44,10 @@ set _smp_command "" | |||
for { set _core 0 } { $_core < $_cores } { incr _core 1 } { | |||
cti create cti$_core -chain-position $_CHIPNAME.dap -ctibase [lindex $_ctis $_core] -ap-num 0 | |||
cti create cti$_core -dap $_CHIPNAME.dap -ctibase [lindex $_ctis $_core] -ap-num 0 | |||
set _command "target create ${_TARGETNAME}$_core aarch64 \ | |||
-chain-position $_CHIPNAME.dap -coreid $_core \ | |||
-dap $_CHIPNAME.dap -coreid $_core \ | |||
-cti cti$_core" | |||
if { $_core != 0 } { | |||
@@ -65,6 +66,6 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } { | |||
eval $_smp_command | |||
# declare the auxiliary Cortex-M3 core on AP #3 | |||
target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 3 -defer-examine | |||
target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine | |||
targets ${_TARGETNAME}0 |
@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -31,9 +31,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -25,9 +25,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
adapter_khz 1000 | |||
@@ -28,8 +28,9 @@ if { [info exists WORKAREASIZE] } { | |||
# Debug Adapter Target Settings | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -20,9 +20,9 @@ if { [info exists DAP_TAPID] } { | |||
} else { | |||
set _DAP_TAPID 0x0b6d602f | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable \ | |||
jtag configure $_CHIPNAME.cpu -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 3" | |||
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan | |||
@@ -36,7 +36,8 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ | |||
# GDB target: Cortex-A8, using DAP | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap | |||
# SRAM: 64K at 0x4020.0000; use the first 16K | |||
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000 | |||
@@ -22,9 +22,9 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x3BA00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable \ | |||
jtag configure $_CHIPNAME.cpu -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 9" | |||
@@ -37,14 +37,14 @@ if { [info exists M3_DAP_TAPID] } { | |||
set _M3_DAP_TAPID 0x4BA00477 | |||
} | |||
jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M3_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.m31_dap -event tap-enable \ | |||
jtag configure $_CHIPNAME.m31 -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 5" | |||
jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M3_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.m30_dap -event tap-enable \ | |||
jtag configure $_CHIPNAME.m30 -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 4" | |||
@@ -93,8 +93,9 @@ set _TARGETNAME $_CHIPNAME.cpu | |||
set _coreid 0 | |||
set _dbgbase [expr 0x80000000 | ($_coreid << 13)] | |||
echo "Using dbgbase = [format 0x%x $_dbgbase]" | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 0 -dbgbase $_dbgbase | |||
# SRAM: 56KiB at 0x4030.0000 | |||
@@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 | |||
# | |||
# M3 targets, separate TAP/DAP for each core | |||
# | |||
target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap | |||
target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap | |||
dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30 | |||
dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31 | |||
target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap | |||
target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap | |||
# Once the JRC is up, enable our TAPs | |||
jtag configure $_CHIPNAME.jrc -event setup " | |||
jtag tapenable $_CHIPNAME.dap | |||
jtag tapenable $_CHIPNAME.m30_dap | |||
jtag tapenable $_CHIPNAME.m31_dap | |||
jtag tapenable $_CHIPNAME.cpu | |||
jtag tapenable $_CHIPNAME.m30 | |||
jtag tapenable $_CHIPNAME.m31 | |||
" | |||
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset | |||
@@ -124,4 +127,3 @@ $_CHIPNAME.m31 configure -event reset-assert { } | |||
# Soft breakpoints don't currently work due to broken cache handling | |||
gdb_breakpoint_override hard | |||
@@ -22,9 +22,9 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x3BA00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable \ | |||
jtag configure $_CHIPNAME.cpu -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 9" | |||
@@ -37,14 +37,14 @@ if { [info exists M3_DAP_TAPID] } { | |||
set _M3_DAP_TAPID 0x4BA00477 | |||
} | |||
jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M3_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.m31_dap -event tap-enable \ | |||
jtag configure $_CHIPNAME.m31 -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 5" | |||
jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \ | |||
-expected-id $_M3_DAP_TAPID -disable | |||
jtag configure $_CHIPNAME.m30_dap -event tap-enable \ | |||
jtag configure $_CHIPNAME.m30 -event tap-enable \ | |||
"icepick_c_tapenable $_CHIPNAME.jrc 4" | |||
@@ -94,7 +94,8 @@ set _coreid 0 | |||
set _dbgbase [expr 0x80000000 | ($_coreid << 13)] | |||
echo "Using dbgbase = [format 0x%x $_dbgbase]" | |||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 0 -dbgbase $_dbgbase | |||
# SRAM: 56KiB at 0x4030.0000 | |||
@@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 | |||
# | |||
# M3 targets, separate TAP/DAP for each core | |||
# | |||
target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap | |||
target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap | |||
dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30 | |||
dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31 | |||
target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap | |||
target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap | |||
# Once the JRC is up, enable our TAPs | |||
jtag configure $_CHIPNAME.jrc -event setup " | |||
jtag tapenable $_CHIPNAME.dap | |||
jtag tapenable $_CHIPNAME.m30_dap | |||
jtag tapenable $_CHIPNAME.m31_dap | |||
jtag tapenable $_CHIPNAME.cpu | |||
jtag tapenable $_CHIPNAME.m30 | |||
jtag tapenable $_CHIPNAME.m31 | |||
" | |||
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset | |||
@@ -26,9 +26,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -23,9 +23,10 @@ if { [using_jtag] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
if {![using_hla]} { | |||
cortex_m reset_config sysresetreq | |||
@@ -19,6 +19,7 @@ global TARGET | |||
set TARGET $_CHIPNAME.cpu | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
# Is CM0 Debugging enabled ? | |||
global _ENABLE_CM0 | |||
@@ -99,7 +100,7 @@ proc psoc6_deassert_post { target } { | |||
} | |||
if { $_ENABLE_CM0 } { | |||
target create ${TARGET}.cm0 cortex_m -chain-position $TARGET -ap-num 1 -coreid 0 | |||
target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 | |||
${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0 | |||
flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0 | |||
@@ -114,7 +115,7 @@ if { $_ENABLE_CM0 } { | |||
} | |||
if { $_ENABLE_CM4 } { | |||
target create ${TARGET}.cm4 cortex_m -chain-position $TARGET -ap-num 2 -coreid 1 | |||
target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 | |||
${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0 | |||
flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4 | |||
@@ -29,9 +29,10 @@ if { [using_jtag] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
if { [info exists WORKAREASIZE] } { | |||
set _WORKAREASIZE $WORKAREASIZE | |||
@@ -38,9 +38,10 @@ if { [info exists WORKAREASIZE] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE | |||
@@ -42,7 +42,8 @@ if { [info exists CPUTAPID] } { | |||
# ... even though SWD ignores all except TAPID, and | |||
# JTAG shouldn't need anything more then irlen. (and TAPID). | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ | |||
-expected-id $_CPUTAPID -ignore-version | |||
-expected-id $_CPUTAPID -ignore-version | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if { [info exists WORKAREASIZE] } { | |||
set _WORKAREASIZE $WORKAREASIZE | |||
@@ -52,7 +53,7 @@ if { [info exists WORKAREASIZE] } { | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
# 8K working area at base of ram, not backed up | |||
# | |||
@@ -32,9 +32,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -49,13 +49,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -49,13 +49,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -34,13 +34,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
swj_newdap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -37,9 +37,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -45,13 +45,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
jtag newtap $_CHIPNAME bs -irlen 5 | |||
} | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -37,6 +37,7 @@ if { [info exists CPUTAPID] } { | |||
set _ENDIAN little | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
if {[using_jtag]} { | |||
if { [info exists BSTAPID] } { | |||
@@ -53,7 +54,7 @@ if {[using_jtag]} { | |||
# Set Target | |||
# | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap | |||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |||
@@ -31,9 +31,10 @@ if { [using_jtag] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
if { [info exists WORKAREASIZE] } { | |||
set _WORKAREASIZE $WORKAREASIZE | |||
@@ -167,11 +167,11 @@ if { [info exists CPUTAPID] } { | |||
} else { | |||
set _CPUTAPID 0x4ba00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable | |||
jtag configure $_CHIPNAME.dap -event tap-enable \ | |||
"u8500_dapenable $_CHIPNAME.dap" | |||
jtag configure $_CHIPNAME.dap -event tap-disable \ | |||
"u8500_tapdisable $_CHIPNAME.dap 0xc0" | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable | |||
jtag configure $_CHIPNAME.cpu -event tap-enable \ | |||
"u8500_dapenable $_CHIPNAME.cpu" | |||
jtag configure $_CHIPNAME.cpu -event tap-disable \ | |||
"u8500_tapdisable $_CHIPNAME.cpu 0xc0" | |||
#CLTAPC TAP JRC equivalent | |||
@@ -202,7 +202,9 @@ if { [info exists DAP_DBG2] } { | |||
set _DAP_DBG2 0x801AA000 | |||
} | |||
target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create $_TARGETNAME_1 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux | |||
$_TARGETNAME_1 configure -event gdb-attach { | |||
halt | |||
@@ -217,7 +219,7 @@ global _TARGETNAME_2 | |||
set _TARGETNAME_2 $TARGETNAME_2 | |||
} | |||
target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux | |||
target create $_TARGETNAME_2 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux | |||
$_TARGETNAME_2 configure -event gdb-attach { | |||
halt | |||
@@ -29,8 +29,9 @@ if { [using_jtag] } { | |||
source [find target/swj-dp.tcl] | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.cpu -dbgbase 0xc0088000 | |||
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000 | |||
adapter_khz 1000 |
@@ -17,7 +17,8 @@ if { [info exists DAP_TAPID] } { | |||
set _DAP_TAPID 0x5ba00477 | |||
} | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID | |||
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap | |||
# | |||
# PS tap | |||
@@ -53,6 +54,7 @@ jtag configure $_CHIPNAME.ps -event setup { | |||
set _TARGETNAME $_CHIPNAME.a53 | |||
set _CTINAME $_CHIPNAME.cti | |||
set _smp_command "" | |||
set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} | |||
set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} | |||
@@ -60,10 +62,10 @@ set _cores 4 | |||
for { set _core 0 } { $_core < $_cores } { incr _core } { | |||
cti create $_CTINAME.$_core -chain-position $_CHIPNAME.dap -ap-num 1 \ | |||
cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ | |||
-ctibase [lindex $CTIBASE $_core] | |||
set _command "target create $_TARGETNAME.$_core aarch64 -chain-position $_CHIPNAME.dap \ | |||
set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ | |||
-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core" | |||
if { $_core != 0 } { | |||
@@ -20,9 +20,10 @@ if { [info exists CPUTAPID] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap | |||
if { [info exists WORKAREASIZE] } { | |||
set _WORKAREASIZE $WORKAREASIZE | |||
@@ -35,9 +35,10 @@ if { [using_jtag] } { | |||
} | |||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
set _TARGETNAME $_CHIPNAME.cpu | |||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME | |||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap | |||
# Work-area is a space in RAM used for flash programming | |||
# By default use 16 kB | |||
@@ -13,11 +13,13 @@ jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \ | |||
-expected-id 0x03727093 \ | |||
-expected-id 0x03736093 | |||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477 | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477 | |||
target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \ | |||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |||
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 0 -dbgbase 0x80090000 | |||
target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \ | |||
target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \ | |||
-coreid 1 -dbgbase 0x80092000 | |||
target smp ${_TARGETNAME}0 ${_TARGETNAME}1 | |||