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@@ -3,7 +3,7 @@ |
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# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ] |
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# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ] |
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proc config {label} { |
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proc config {label} { |
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return [dict get [configC100] $label ] |
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return [dict get [configC100] $label ] |
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} |
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} |
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# show the value for the param. with label |
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# show the value for the param. with label |
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@@ -15,7 +15,7 @@ proc showconfig {label} { |
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# when there are more then one board config |
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# when there are more then one board config |
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# use soft links to c100board-config.tcl |
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# use soft links to c100board-config.tcl |
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# so that only the right board-config gets |
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# so that only the right board-config gets |
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# included (just like include/configs/board-configs.h |
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# included (just like include/configs/board-configs.h |
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# in u-boot. |
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# in u-boot. |
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proc configC100 {} { |
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proc configC100 {} { |
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# xtal freq. 24MHz |
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# xtal freq. 24MHz |
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@@ -28,7 +28,7 @@ proc configC100 {} { |
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# y = amba_clk * (w+1)*(x+1)*2/xtal_clk |
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# y = amba_clk * (w+1)*(x+1)*2/xtal_clk |
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dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] |
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dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] |
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# Arm Clk 450MHz, must be a multiple of 25 MHz |
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# Arm Clk 450MHz, must be a multiple of 25 MHz |
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dict set configC100 CFG_ARM_CLOCK 450000000 |
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dict set configC100 CFG_ARM_CLOCK 450000000 |
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dict set configC100 w_arm 0 |
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dict set configC100 w_arm 0 |
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dict set configC100 x_arm 1 |
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dict set configC100 x_arm 1 |
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@@ -44,7 +44,7 @@ proc setupTelo {} { |
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# setup GPIO used as control signals for C100 |
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# setup GPIO used as control signals for C100 |
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setupGPIO |
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setupGPIO |
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# This will allow acces to lower 8MB or NOR |
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# This will allow acces to lower 8MB or NOR |
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lowGPIO5 |
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lowGPIO5 |
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# setup NOR size,timing,etc. |
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# setup NOR size,timing,etc. |
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setupNOR |
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setupNOR |
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# setup internals + PLL + DDR2 |
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# setup internals + PLL + DDR2 |
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@@ -55,17 +55,17 @@ proc setupTelo {} { |
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proc setupNOR {} { |
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proc setupNOR {} { |
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puts "Setting up NOR: 16MB, 16-bit wide bus, CS0" |
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puts "Setting up NOR: 16MB, 16-bit wide bus, CS0" |
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# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init() |
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# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init() |
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set EX_CSEN_REG [regs EX_CSEN_REG ] |
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set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] |
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set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] |
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set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] |
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set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] |
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set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] |
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set EX_CSEN_REG [regs EX_CSEN_REG ] |
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set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] |
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set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] |
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set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] |
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set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] |
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set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] |
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set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] |
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set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] |
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set EX_MFSM_REG [regs EX_MFSM_REG ] |
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set EX_CSFSM_REG [regs EX_CSFSM_REG ] |
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set EX_WRFSM_REG [regs EX_WRFSM_REG ] |
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set EX_RDFSM_REG [regs EX_RDFSM_REG ] |
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set EX_MFSM_REG [regs EX_MFSM_REG ] |
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set EX_CSFSM_REG [regs EX_CSFSM_REG ] |
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set EX_WRFSM_REG [regs EX_WRFSM_REG ] |
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set EX_RDFSM_REG [regs EX_RDFSM_REG ] |
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# enable Expansion Bus Clock + CS0 (NOR) |
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# enable Expansion Bus Clock + CS0 (NOR) |
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mww $EX_CSEN_REG 0x3 |
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mww $EX_CSEN_REG 0x3 |
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@@ -76,7 +76,7 @@ proc setupNOR {} { |
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# set timings to NOR |
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# set timings to NOR |
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mww $EX_CS0_TMG1_REG 0x03034006 |
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mww $EX_CS0_TMG1_REG 0x03034006 |
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mww $EX_CS0_TMG2_REG 0x04040002 |
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mww $EX_CS0_TMG2_REG 0x04040002 |
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#mww $EX_CS0_TMG3_REG |
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#mww $EX_CS0_TMG3_REG |
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# set EBUS clock 165/5=33MHz |
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# set EBUS clock 165/5=33MHz |
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mww $EX_CLOCK_DIV_REG 0x5 |
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mww $EX_CLOCK_DIV_REG 0x5 |
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# everthing else is OK with default |
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# everthing else is OK with default |
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@@ -86,7 +86,7 @@ proc bootNOR {} { |
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] |
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] |
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set BLOCK_RESET_REG [regs BLOCK_RESET_REG] |
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set BLOCK_RESET_REG [regs BLOCK_RESET_REG] |
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set DDR_RST [regs DDR_RST] |
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set DDR_RST [regs DDR_RST] |
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# put DDR controller in reset (so that it comes reset in u-boot) |
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# put DDR controller in reset (so that it comes reset in u-boot) |
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mmw $BLOCK_RESET_REG 0x0 $DDR_RST |
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mmw $BLOCK_RESET_REG 0x0 $DDR_RST |
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# setup CS0 controller for NOR |
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# setup CS0 controller for NOR |
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@@ -107,8 +107,8 @@ proc setupGPIO {} { |
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#GPIO17 reset for DECT module. |
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#GPIO17 reset for DECT module. |
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#GPIO29 CS_n for NAND |
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#GPIO29 CS_n for NAND |
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] |
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set GPIO_OE_REG [regs GPIO_OE_REG] |
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] |
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set GPIO_OE_REG [regs GPIO_OE_REG] |
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# set GPIO29=GPIO17=1, GPIO5=0 |
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# set GPIO29=GPIO17=1, GPIO5=0 |
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mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] |
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mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] |
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@@ -118,14 +118,14 @@ proc setupGPIO {} { |
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proc highGPIO5 {} { |
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proc highGPIO5 {} { |
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puts "GPIO5 high" |
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puts "GPIO5 high" |
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] |
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] |
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# set GPIO5=1 |
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# set GPIO5=1 |
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mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 |
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mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 |
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} |
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} |
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proc lowGPIO5 {} { |
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proc lowGPIO5 {} { |
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puts "GPIO5 low" |
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puts "GPIO5 low" |
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] |
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set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] |
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# set GPIO5=0 |
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# set GPIO5=0 |
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mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] |
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mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] |
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} |
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} |
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@@ -133,21 +133,21 @@ proc lowGPIO5 {} { |
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proc boardID {id} { |
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proc boardID {id} { |
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# so far built: |
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# so far built: |
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# 4'b1111 |
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# 4'b1111 |
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dict set boardID 15 name "EVT1" |
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dict set boardID 15 name "EVT1" |
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dict set boardID 15 ddr2size 128M |
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dict set boardID 15 ddr2size 128M |
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# dict set boardID 15 nandsize 1G |
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# dict set boardID 15 nandsize 1G |
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# dict set boardID 15 norsize 16M |
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# dict set boardID 15 norsize 16M |
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# 4'b0000 |
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# 4'b0000 |
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dict set boardID 0 name "EVT2" |
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dict set boardID 0 name "EVT2" |
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dict set boardID 0 ddr2size 128M |
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dict set boardID 0 ddr2size 128M |
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# 4'b0001 |
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# 4'b0001 |
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dict set boardID 1 name "EVT3" |
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dict set boardID 1 name "EVT3" |
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dict set boardID 1 ddr2size 256M |
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dict set boardID 1 ddr2size 256M |
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# 4'b1110 |
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# 4'b1110 |
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dict set boardID 14 name "EVT3_old" |
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dict set boardID 14 name "EVT3_old" |
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dict set boardID 14 ddr2size 128M |
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dict set boardID 14 ddr2size 128M |
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# 4'b0010 |
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# 4'b0010 |
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dict set boardID 2 name "EVT4" |
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dict set boardID 2 name "EVT4" |
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dict set boardID 2 ddr2size 256M |
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dict set boardID 2 ddr2size 256M |
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return $boardID |
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return $boardID |
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@@ -155,10 +155,10 @@ proc boardID {id} { |
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# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect() |
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# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect() |
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# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors |
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# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors |
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proc ooma_board_detect {} { |
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proc ooma_board_detect {} { |
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set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] |
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set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] |
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# read the current value of the BOOTSRAP pins |
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# read the current value of the BOOTSRAP pins |
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set tmp [mrw $GPIO_BOOTSTRAP_REG] |
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set tmp [mrw $GPIO_BOOTSTRAP_REG] |
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puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] |
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puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] |
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@@ -174,7 +174,7 @@ proc ooma_board_detect {} { |
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} |
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} |
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proc configureDDR2regs_256M {} { |
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proc configureDDR2regs_256M {} { |
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set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] |
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set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] |
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set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] |
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set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] |
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set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] |
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set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] |
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@@ -208,7 +208,7 @@ proc configureDDR2regs_256M {} { |
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mw64bit $DENALI_CTL_04_DATA 0x0000010100000001 |
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mw64bit $DENALI_CTL_04_DATA 0x0000010100000001 |
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mw64bit $DENALI_CTL_05_DATA 0x0203010300010101 |
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mw64bit $DENALI_CTL_05_DATA 0x0203010300010101 |
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mw64bit $DENALI_CTL_06_DATA 0x060a020200020202 |
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mw64bit $DENALI_CTL_06_DATA 0x060a020200020202 |
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mw64bit $DENALI_CTL_07_DATA 0x0000000300000206 |
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mw64bit $DENALI_CTL_07_DATA 0x0000000300000206 |
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mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209 |
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mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209 |
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mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a |
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mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a |
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mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18 |
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mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18 |
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@@ -222,15 +222,15 @@ proc configureDDR2regs_256M {} { |
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mw64bit $DENALI_CTL_17_DATA 0x0000000000000000 |
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mw64bit $DENALI_CTL_17_DATA 0x0000000000000000 |
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mw64bit $DENALI_CTL_18_DATA 0x0302000000000000 |
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mw64bit $DENALI_CTL_18_DATA 0x0302000000000000 |
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mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600 |
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mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600 |
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mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8 |
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mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8 |
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set wr_dqs_shift 0x40 |
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set wr_dqs_shift 0x40 |
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# start DDRC |
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# start DDRC |
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mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] |
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mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] |
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# wait int_status[2] (DRAM init complete) |
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# wait int_status[2] (DRAM init complete) |
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puts -nonewline "Waiting for DDR2 controller to init..." |
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puts -nonewline "Waiting for DDR2 controller to init..." |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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while { [expr $tmp & 0x040000] == 0 } { |
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while { [expr $tmp & 0x040000] == 0 } { |
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sleep 1 |
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sleep 1 |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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} |
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} |
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@@ -267,9 +267,9 @@ proc configureDDR2regs_128M {} { |
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set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] |
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set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] |
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set DENALI_CTL_02_VAL 0x0100010000010100 |
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set DENALI_CTL_02_VAL 0x0100010000010100 |
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set DENALI_CTL_11_VAL 0x433A42124A650A37 |
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set DENALI_CTL_11_VAL 0x433A42124A650A37 |
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# set some default values |
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# set some default values |
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mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 |
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mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 |
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mw64bit $DENALI_CTL_01_DATA 0x0100000100000101 |
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mw64bit $DENALI_CTL_01_DATA 0x0100000100000101 |
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mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL |
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mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL |
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@@ -298,7 +298,7 @@ proc configureDDR2regs_128M {} { |
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# wait int_status[2] (DRAM init complete) |
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# wait int_status[2] (DRAM init complete) |
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puts -nonewline "Waiting for DDR2 controller to init..." |
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puts -nonewline "Waiting for DDR2 controller to init..." |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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while { [expr $tmp & 0x040000] == 0 } { |
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while { [expr $tmp & 0x040000] == 0 } { |
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sleep 1 |
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sleep 1 |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] |
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} |
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} |
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@@ -318,18 +318,18 @@ proc setupUART0 {} { |
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set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] |
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set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] |
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set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] |
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set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] |
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set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0] |
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set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0] |
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set UART0_LCR [regs UART0_LCR] |
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set LCR_DLAB [regs LCR_DLAB] |
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set UART0_DLL [regs UART0_DLL] |
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set UART0_DLH [regs UART0_DLH] |
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set UART0_IIR [regs UART0_IIR] |
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set UART0_IER [regs UART0_IER] |
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set LCR_ONE_STOP [regs LCR_ONE_STOP] |
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set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] |
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set UART0_LCR [regs UART0_LCR] |
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set LCR_DLAB [regs LCR_DLAB] |
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set UART0_DLL [regs UART0_DLL] |
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set UART0_DLH [regs UART0_DLH] |
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set UART0_IIR [regs UART0_IIR] |
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set UART0_IER [regs UART0_IER] |
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set LCR_ONE_STOP [regs LCR_ONE_STOP] |
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set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] |
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set FCR_XMITRES [regs FCR_XMITRES] |
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set FCR_XMITRES [regs FCR_XMITRES] |
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set FCR_RCVRRES [regs FCR_RCVRRES] |
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set FCR_FIFOEN [regs FCR_FIFOEN] |
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set IER_UUE [regs IER_UUE] |
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set FCR_RCVRRES [regs FCR_RCVRRES] |
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set FCR_FIFOEN [regs FCR_FIFOEN] |
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set IER_UUE [regs IER_UUE] |
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# unlock writing to IOCTRL register |
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# unlock writing to IOCTRL register |
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mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL |
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mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL |
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@@ -355,7 +355,7 @@ proc setupUART0 {} { |
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proc putcUART0 {char} { |
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proc putcUART0 {char} { |
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set UART0_LSR [regs UART0_LSR] |
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set UART0_LSR [regs UART0_LSR] |
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set UART0_THR [regs UART0_THR] |
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set UART0_THR [regs UART0_THR] |
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set LSR_TEMT [regs LSR_TEMT] |
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set LSR_TEMT [regs LSR_TEMT] |
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@@ -392,7 +392,7 @@ proc trainDDR2 {} { |
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proc flashUBOOT {file} { |
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proc flashUBOOT {file} { |
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# this will update uboot on NOR partition |
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# this will update uboot on NOR partition |
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] |
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set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] |
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# setup CS0 controller for NOR |
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# setup CS0 controller for NOR |
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setupNOR |
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setupNOR |
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# make sure we are accessing the lower part of NOR |
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# make sure we are accessing the lower part of NOR |
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