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@@ -1607,7 +1607,6 @@ static int arm7_9_restore_context(struct target *target) |
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target); |
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target); |
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struct arm *armv4_5 = &arm7_9->armv4_5_common; |
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struct arm *armv4_5 = &arm7_9->armv4_5_common; |
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struct reg *reg; |
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struct reg *reg; |
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struct arm_reg *reg_arch_info; |
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enum arm_mode current_mode = armv4_5->core_mode; |
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enum arm_mode current_mode = armv4_5->core_mode; |
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int i, j; |
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int i, j; |
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int dirty; |
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int dirty; |
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@@ -1644,13 +1643,14 @@ static int arm7_9_restore_context(struct target *target) |
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for (j = 0; j <= 16; j++) |
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for (j = 0; j <= 16; j++) |
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{ |
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{ |
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reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); |
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reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); |
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reg_arch_info = reg->arch_info; |
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if (reg->dirty == 1) |
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if (reg->dirty == 1) |
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{ |
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{ |
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if (reg->valid == 1) |
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if (reg->valid == 1) |
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{ |
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{ |
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dirty = 1; |
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dirty = 1; |
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LOG_DEBUG("examining dirty reg: %s", reg->name); |
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LOG_DEBUG("examining dirty reg: %s", reg->name); |
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struct arm_reg *reg_arch_info; |
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reg_arch_info = reg->arch_info; |
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if ((reg_arch_info->mode != ARM_MODE_ANY) |
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if ((reg_arch_info->mode != ARM_MODE_ANY) |
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&& (reg_arch_info->mode != current_mode) |
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&& (reg_arch_info->mode != current_mode) |
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&& !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS)) |
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&& !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS)) |
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@@ -1689,8 +1689,6 @@ static int arm7_9_restore_context(struct target *target) |
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for (j = 0; j <= 14; j++) |
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for (j = 0; j <= 14; j++) |
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{ |
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{ |
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reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); |
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reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); |
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reg_arch_info = reg->arch_info; |
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if (reg->dirty == 1) |
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if (reg->dirty == 1) |
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{ |
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{ |
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@@ -1712,6 +1710,7 @@ static int arm7_9_restore_context(struct target *target) |
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} |
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} |
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reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16); |
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reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16); |
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struct arm_reg *reg_arch_info; |
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reg_arch_info = reg->arch_info; |
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reg_arch_info = reg->arch_info; |
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if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) |
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if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) |
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{ |
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{ |
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@@ -1823,7 +1822,6 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand |
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{ |
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{ |
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target); |
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target); |
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struct arm *armv4_5 = &arm7_9->armv4_5_common; |
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struct arm *armv4_5 = &arm7_9->armv4_5_common; |
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struct breakpoint *breakpoint = target->breakpoints; |
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struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; |
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struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; |
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int err, retval = ERROR_OK; |
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int err, retval = ERROR_OK; |
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@@ -1850,6 +1848,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand |
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/* the front-end may request us not to handle breakpoints */ |
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/* the front-end may request us not to handle breakpoints */ |
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if (handle_breakpoints) |
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if (handle_breakpoints) |
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{ |
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{ |
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struct breakpoint *breakpoint; |
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breakpoint = breakpoint_find(target, |
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breakpoint = breakpoint_find(target, |
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buf_get_u32(armv4_5->pc->value, 0, 32)); |
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buf_get_u32(armv4_5->pc->value, 0, 32)); |
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if (breakpoint != NULL) |
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if (breakpoint != NULL) |
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@@ -2135,7 +2134,6 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, |
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int num, enum arm_mode mode) |
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int num, enum arm_mode mode) |
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{ |
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{ |
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uint32_t* reg_p[16]; |
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uint32_t* reg_p[16]; |
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uint32_t value; |
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int retval; |
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int retval; |
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struct arm_reg *areg = r->arch_info; |
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struct arm_reg *areg = r->arch_info; |
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target); |
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target); |
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@@ -2159,6 +2157,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, |
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arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); |
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arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); |
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} |
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} |
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uint32_t value = 0; |
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if ((num >= 0) && (num <= 15)) |
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if ((num >= 0) && (num <= 15)) |
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{ |
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{ |
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/* read a normal core register */ |
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/* read a normal core register */ |
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