Browse Source

build: cleanup src/target directory

Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/430
Tested-by: jenkins
tags/v0.6.0-rc1
Spencer Oliver 10 years ago
parent
commit
374127301e
100 changed files with 8704 additions and 10798 deletions
  1. +18
    -24
      src/target/adi_v5_jtag.c
  2. +10
    -14
      src/target/adi_v5_swd.c
  3. +1
    -1
      src/target/algorithm.c
  4. +4
    -6
      src/target/algorithm.h
  5. +1
    -0
      src/target/arm.h
  6. +259
    -308
      src/target/arm11.c
  7. +24
    -29
      src/target/arm11.h
  8. +280
    -292
      src/target/arm11_dbgtap.c
  9. +26
    -5
      src/target/arm11_dbgtap.h
  10. +34
    -63
      src/target/arm720t.c
  11. +4
    -6
      src/target/arm720t.h
  12. +569
    -735
      src/target/arm7_9_common.c
  13. +44
    -24
      src/target/arm7_9_common.h
  14. +35
    -58
      src/target/arm7tdmi.c
  15. +1
    -0
      src/target/arm7tdmi.h
  16. +222
    -303
      src/target/arm920t.c
  17. +6
    -10
      src/target/arm920t.h
  18. +44
    -78
      src/target/arm926ejs.c
  19. +8
    -9
      src/target/arm926ejs.h
  20. +87
    -136
      src/target/arm946e.c
  21. +6
    -7
      src/target/arm946e.h
  22. +20
    -30
      src/target/arm966e.c
  23. +2
    -2
      src/target/arm966e.h
  24. +46
    -97
      src/target/arm9tdmi.c
  25. +2
    -1
      src/target/arm9tdmi.h
  26. +119
    -217
      src/target/arm_adi_v5.c
  27. +8
    -11
      src/target/arm_adi_v5.h
  28. +1669
    -1657
      src/target/arm_disassembler.c
  29. +9
    -16
      src/target/arm_disassembler.h
  30. +155
    -156
      src/target/arm_dpm.c
  31. +1
    -1
      src/target/arm_dpm.h
  32. +8
    -12
      src/target/arm_jtag.c
  33. +10
    -17
      src/target/arm_jtag.h
  34. +3
    -3
      src/target/arm_opcodes.h
  35. +7
    -15
      src/target/arm_semihosting.c
  36. +101
    -237
      src/target/arm_simulator.c
  37. +2
    -2
      src/target/arm_simulator.h
  38. +233
    -249
      src/target/armv4_5.c
  39. +2
    -1
      src/target/armv4_5.h
  40. +8
    -18
      src/target/armv4_5_cache.c
  41. +4
    -6
      src/target/armv4_5_cache.h
  42. +31
    -36
      src/target/armv4_5_mmu.c
  43. +3
    -4
      src/target/armv4_5_mmu.h
  44. +232
    -239
      src/target/armv7a.c
  45. +15
    -24
      src/target/armv7a.h
  46. +110
    -115
      src/target/armv7m.c
  47. +10
    -16
      src/target/armv7m.h
  48. +103
    -136
      src/target/avr32_ap7k.c
  49. +3
    -5
      src/target/avr32_ap7k.h
  50. +16
    -29
      src/target/avr32_jtag.c
  51. +2
    -4
      src/target/avr32_jtag.h
  52. +51
    -65
      src/target/avr32_mem.c
  53. +7
    -7
      src/target/avr32_mem.h
  54. +9
    -8
      src/target/avr32_regs.c
  55. +1
    -1
      src/target/avr32_regs.h
  56. +21
    -27
      src/target/avrt.c
  57. +3
    -4
      src/target/avrt.h
  58. +137
    -165
      src/target/breakpoints.c
  59. +7
    -10
      src/target/breakpoints.h
  60. +449
    -592
      src/target/cortex_a.c
  61. +5
    -7
      src/target/cortex_a.h
  62. +341
    -460
      src/target/cortex_m.c
  63. +6
    -11
      src/target/cortex_m.h
  64. +690
    -654
      src/target/dsp563xx.c
  65. +6
    -8
      src/target/dsp563xx.h
  66. +61
    -50
      src/target/dsp563xx_once.c
  67. +2
    -2
      src/target/dsp563xx_once.h
  68. +9
    -8
      src/target/dsp5680xx.c
  69. +67
    -53
      src/target/dsp5680xx.h
  70. +29
    -31
      src/target/embeddedice.c
  71. +15
    -23
      src/target/embeddedice.h
  72. +56
    -93
      src/target/etb.c
  73. +5
    -7
      src/target/etb.h
  74. +307
    -428
      src/target/etm.c
  75. +13
    -21
      src/target/etm.h
  76. +5
    -11
      src/target/etm_dummy.c
  77. +1
    -0
      src/target/etm_dummy.h
  78. +9
    -15
      src/target/fa526.c
  79. +20
    -34
      src/target/feroceon.c
  80. +245
    -364
      src/target/image.c
  81. +11
    -18
      src/target/image.h
  82. +86
    -148
      src/target/mips32.c
  83. +14
    -18
      src/target/mips32.h
  84. +35
    -41
      src/target/mips32_dmaacc.c
  85. +1
    -0
      src/target/mips32_dmaacc.h
  86. +495
    -540
      src/target/mips32_pracc.c
  87. +3
    -2
      src/target/mips32_pracc.h
  88. +45
    -51
      src/target/mips_ejtag.c
  89. +2
    -3
      src/target/mips_ejtag.h
  90. +159
    -269
      src/target/mips_m4k.c
  91. +1
    -2
      src/target/mips_m4k.h
  92. +30
    -62
      src/target/oocd_trace.c
  93. +4
    -6
      src/target/oocd_trace.h
  94. +5
    -6
      src/target/register.c
  95. +6
    -8
      src/target/register.h
  96. +12
    -22
      src/target/smp.c
  97. +2
    -0
      src/target/smp.h
  98. +30
    -37
      src/target/stm32_stlink.c
  99. +530
    -892
      src/target/target.c
  100. +39
    -50
      src/target/target.h

+ 18
- 24
src/target/adi_v5_jtag.c View File

@@ -40,7 +40,6 @@
#include "arm_adi_v5.h"
#include <helper/time_support.h>


/* JTAG instructions/registers for JTAG-DP and SWJ-DP */
#define JTAG_DP_ABORT 0x8
#define JTAG_DP_DPACC 0xA
@@ -223,22 +222,19 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
if (retval != ERROR_OK)
return retval;
if ((retval = jtag_execute_queue()) != ERROR_OK)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;

dap->ack = dap->ack & 0x7;

/* common code path avoids calling timeval_ms() */
if (dap->ack != JTAG_ACK_OK_FAULT)
{
if (dap->ack != JTAG_ACK_OK_FAULT) {
long long then = timeval_ms();

while (dap->ack != JTAG_ACK_OK_FAULT)
{
if (dap->ack == JTAG_ACK_WAIT)
{
if ((timeval_ms()-then) > 1000)
{
while (dap->ack != JTAG_ACK_OK_FAULT) {
if (dap->ack == JTAG_ACK_WAIT) {
if ((timeval_ms()-then) > 1000) {
/* NOTE: this would be a good spot
* to use JTAG_DP_ABORT.
*/
@@ -247,9 +243,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
"in JTAG-DP transaction");
return ERROR_JTAG_DEVICE_ERROR;
}
}
else
{
} else {
LOG_WARNING("Invalid ACK %#x "
"in JTAG-DP transaction",
dap->ack);
@@ -260,7 +254,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
if (retval != ERROR_OK)
return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
dap->ack = dap->ack & 0x7;
}
@@ -269,18 +264,14 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
/* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */

/* Check for STICKYERR and STICKYORUN */
if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
{
if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
{
if ((ctrlstat & 0xf0000000) != 0xf0000000) {
retval = ahbap_debugport_init(dap);
if (retval != ERROR_OK)
return retval;
}
else
{
} else {
uint32_t mem_ap_csw, mem_ap_tar;

/* Maybe print information about last intended
@@ -314,7 +305,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
if (retval != ERROR_OK)
return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;

LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
@@ -329,13 +321,15 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
if (retval != ERROR_OK)
return retval;

if ((retval = dap_run(dap)) != ERROR_OK)
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
PRIx32, mem_ap_csw, mem_ap_tar);

}
if ((retval = dap_run(dap)) != ERROR_OK)
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
return ERROR_JTAG_DEVICE_ERROR;
}


+ 10
- 14
src/target/adi_v5_swd.c View File

@@ -55,12 +55,10 @@

#include <jtag/swd.h>



static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
// REVISIT status return vs ack ...
/* REVISIT status return vs ack ... */
return swd->read_reg(swd_cmd(true, false, reg), data);
}

@@ -71,14 +69,14 @@ static int swd_queue_idcode_read(struct adiv5_dap *dap,
if (status < 0)
return status;
*ack = status;
// ??
/* ?? */
return ERROR_OK;
}

static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
// REVISIT status return vs ack ...
/* REVISIT status return vs ack ... */
return swd->write_reg(swd_cmd(false, false, reg), data);
}

@@ -86,16 +84,16 @@ static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
// REVISIT APSEL ...
// REVISIT status return ...
/* REVISIT APSEL ... */
/* REVISIT status return ... */
return swd->read_reg(swd_cmd(true, true, reg), data);
}

static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
// REVISIT APSEL ...
// REVISIT status return ...
/* REVISIT APSEL ... */
/* REVISIT status return ... */
return swd->write_reg(swd_cmd(false, true, reg), data);
}

@@ -194,15 +192,14 @@ COMMAND_HANDLER(handle_swd_wcr)
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm *arm = target_to_arm(target);
struct adiv5_dap *dap = arm->dap;
struct adiv5_dap *dap = arm->dap;
uint32_t wcr;
unsigned trn, scale = 0;


switch (CMD_ARGC) {
/* no-args: just dump state */
case 0:
//retval = swd_queue_dp_read(dap, DP_WCR, &wcr);
/*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
if (retval == ERROR_OK)
dap->ops->run(dap);
@@ -315,11 +312,10 @@ static int swd_init(struct command_context *ctx)
{
struct target *target = get_current_target(ctx);
struct arm *arm = target_to_arm(target);
struct adiv5_dap *dap = arm->dap;
struct adiv5_dap *dap = arm->dap;
uint32_t idcode;
int status;


/* FIXME validate transport config ... is the
* configured DAP present (check IDCODE)?
* Is *only* one DAP configured?


+ 1
- 1
src/target/algorithm.c View File

@@ -17,6 +17,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -24,7 +25,6 @@
#include "algorithm.h"
#include <helper/binarybuffer.h>


void init_mem_param(struct mem_param *param, uint32_t address, uint32_t size, enum param_direction direction)
{
param->address = address;


+ 4
- 6
src/target/algorithm.h View File

@@ -17,26 +17,24 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifndef ALGORITHM_H
#define ALGORITHM_H

enum param_direction
{
enum param_direction {
PARAM_IN,
PARAM_OUT,
PARAM_IN_OUT
};

struct mem_param
{
struct mem_param {
uint32_t address;
uint32_t size;
uint8_t *value;
enum param_direction direction;
};

struct reg_param
{
struct reg_param {
const char *reg_name;
uint32_t size;
uint8_t *value;


+ 1
- 0
src/target/arm.h View File

@@ -23,6 +23,7 @@
* Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/

#ifndef ARM_H
#define ARM_H



+ 259
- 308
src/target/arm11.c
File diff suppressed because it is too large
View File


+ 24
- 29
src/target/arm11.h View File

@@ -26,38 +26,36 @@
#include "arm.h"
#include "arm_dpm.h"

#define ARM11_TAP_DEFAULT TAP_INVALID
#define ARM11_TAP_DEFAULT TAP_INVALID

#define CHECK_RETVAL(action) \
do { \
int __retval = (action); \
if (__retval != ERROR_OK) { \
LOG_DEBUG("error while calling \"%s\"", \
# action ); \
# action); \
return __retval; \
} \
} while (0)

/* bits from ARMv7 DIDR */
enum arm11_debug_version
{
ARM11_DEBUG_V6 = 0x01,
ARM11_DEBUG_V61 = 0x02,
ARM11_DEBUG_V7 = 0x03,
ARM11_DEBUG_V7_CP14 = 0x04,
enum arm11_debug_version {
ARM11_DEBUG_V6 = 0x01,
ARM11_DEBUG_V61 = 0x02,
ARM11_DEBUG_V7 = 0x03,
ARM11_DEBUG_V7_CP14 = 0x04,
};

struct arm11_common
{
struct arm arm;
struct arm11_common {
struct arm arm;

/** Debug module state. */
struct arm_dpm dpm;
struct arm11_sc7_action *bpwp_actions;
unsigned bpwp_n;

size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t free_brps; /**< Number of breakpoints allocated */
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t free_brps; /**< Number of breakpoints allocated */

uint32_t dscr; /**< Last retrieved DSCR value. */

@@ -67,7 +65,7 @@ struct arm11_common
bool is_rdtr_saved;
bool is_wdtr_saved;

bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt **/

/* Per-core configurable options.
* NOTE that several of these boolean options should not exist
@@ -86,8 +84,7 @@ struct arm11_common

static inline struct arm11_common *target_to_arm11(struct target *target)
{
return container_of(target->arch_info, struct arm11_common,
arm);
return container_of(target->arch_info, struct arm11_common, arm);
}

/**
@@ -95,27 +92,25 @@ static inline struct arm11_common *target_to_arm11(struct target *target)
*
* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
*/
enum arm11_instructions
{
enum arm11_instructions {
ARM11_EXTEST = 0x00,
ARM11_SCAN_N = 0x02,
ARM11_RESTART = 0x04,
ARM11_HALT = 0x08,
ARM11_HALT = 0x08,
ARM11_INTEST = 0x0C,
ARM11_ITRSEL = 0x1D,
ARM11_IDCODE = 0x1E,
ARM11_BYPASS = 0x1F,
};

enum arm11_sc7
{
ARM11_SC7_NULL = 0,
ARM11_SC7_VCR = 7,
ARM11_SC7_PC = 8,
ARM11_SC7_BVR0 = 64,
ARM11_SC7_BCR0 = 80,
ARM11_SC7_WVR0 = 96,
ARM11_SC7_WCR0 = 112,
enum arm11_sc7 {
ARM11_SC7_NULL = 0,
ARM11_SC7_VCR = 7,
ARM11_SC7_PC = 8,
ARM11_SC7_BVR0 = 64,
ARM11_SC7_BCR0 = 80,
ARM11_SC7_WVR0 = 96,
ARM11_SC7_WCR0 = 112,
};

#endif /* ARM11_H */
#endif /* ARM11_H */

+ 280
- 292
src/target/arm11_dbgtap.c
File diff suppressed because it is too large
View File


+ 26
- 5
src/target/arm11_dbgtap.h View File

@@ -1,3 +1,25 @@
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
* Michael Bruck *
* *
* Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifndef ARM11_DBGTAP_H
#define ARM11_DBGTAP_H

@@ -37,10 +59,9 @@ void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_fiel
* Used with arm11_sc7_run to make a list of read/write commands for
* scan chain 7
*/
struct arm11_sc7_action
{
bool write; /**< Access mode: true for write, false for read. */
uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */
struct arm11_sc7_action {
bool write; /**< Access mode: true for write, false for read. */
uint8_t address;/**< Register address mode. Use enum #arm11_sc7 */
/**
* If write then set this to value to be written. In read mode
* this receives the read value when the function returns.
@@ -61,4 +82,4 @@ int arm11_read_memory_word(struct arm11_common *arm11,
int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr);
int arm11_bpwp_flush(struct arm11_common *arm11);

#endif // ARM11_DBGTAP_H
#endif /* ARM11_DBGTAP_H */

+ 34
- 63
src/target/arm720t.c View File

@@ -20,6 +20,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -54,14 +55,12 @@ static int arm720t_scan_cp15(struct target *target,

buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));

if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;
}
if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
{
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;
}

fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf;
@@ -71,24 +70,20 @@ static int arm720t_scan_cp15(struct target *target,
fields[1].out_value = out_buf;
fields[1].in_value = NULL;

if (in)
{
if (in) {
fields[1].in_value = (uint8_t *)in;
jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
} else
{
jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
}

if (clock_arg)
jtag_add_runtest(0, TAP_DRPAUSE);

#ifdef _DEBUG_INSTRUCTION_EXECUTION_
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

if (in)
LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
@@ -254,8 +249,7 @@ static int arm720t_arch_state(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);

static const char *state[] =
{
static const char *state[] = {
"disabled", "enabled"
};

@@ -300,16 +294,14 @@ static int arm720t_read_memory(struct target *target,
struct arm720t_common *arm720t = target_to_arm720(target);

/* disable cache, but leave MMU enabled */
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
if (retval != ERROR_OK)
return retval;
}
retval = arm7_9_read_memory(target, address, size, count, buffer);

if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
if (retval != ERROR_OK)
return retval;
@@ -342,36 +334,26 @@ static int arm720t_soft_reset_halt(struct target *target)
.eice_cache->reg_list[EICE_DBG_STAT];
struct arm *arm = &arm720t->arm7_9_common.arm;

if ((retval = target_halt(target)) != ERROR_OK)
{
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
}

long long then = timeval_ms();
int timeout;
while (!(timeout = ((timeval_ms()-then) > 1000)))
{
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
while (!(timeout = ((timeval_ms()-then) > 1000))) {
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
embeddedice_read_reg(dbg_stat);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}
} else
{
break;
}
if (debug_level >= 3)
{
alive_sleep(100);
} else
{
else
keep_alive();
}
}
if (timeout)
{
if (timeout) {
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
@@ -399,10 +381,9 @@ static int arm720t_soft_reset_halt(struct target *target)
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;

if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
if (retval != ERROR_OK)
return retval;
}

return ERROR_OK;
}
@@ -467,42 +448,35 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
if (retval != ERROR_OK)
return retval;


if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED) {
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}

/* one or more argument, access a single register (write if second argument is given */
if (CMD_ARGC >= 1)
{
if (CMD_ARGC >= 1) {
uint32_t opcode;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);

if (CMD_ARGC == 1)
{
if (CMD_ARGC == 1) {
uint32_t value;
if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
{
retval = arm720t_read_cp15(target, opcode, &value);
if (retval != ERROR_OK) {
command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
return ERROR_OK;
}

if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
}
else if (CMD_ARGC == 2)
{
} else if (CMD_ARGC == 2) {
uint32_t value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);

if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
{
retval = arm720t_write_cp15(target, opcode, value);
if (retval != ERROR_OK) {
command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
return ERROR_OK;
}
@@ -518,8 +492,7 @@ static int arm720t_mrc(struct target *target, int cpnum,
uint32_t CRn, uint32_t CRm,
uint32_t *value)
{
if (cpnum!=15)
{
if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
@@ -536,8 +509,7 @@ static int arm720t_mcr(struct target *target, int cpnum,
uint32_t CRn, uint32_t CRm,
uint32_t value)
{
if (cpnum!=15)
{
if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
@@ -576,8 +548,7 @@ static const struct command_registration arm720t_command_handlers[] = {
};

/** Holds methods for ARM720 targets. */
struct target_type arm720t_target =
{
struct target_type arm720t_target = {
.name = "arm720t",

.poll = arm7_9_poll,


+ 4
- 6
src/target/arm720t.h View File

@@ -17,6 +17,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifndef ARM720T_H
#define ARM720T_H

@@ -25,8 +26,7 @@

#define ARM720T_COMMON_MAGIC 0xa720a720

struct arm720t_common
{
struct arm720t_common {
struct arm7_9_common arm7_9_common;
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
@@ -35,11 +35,9 @@ struct arm720t_common
uint32_t far_reg;
};

static inline struct arm720t_common *
target_to_arm720(struct target *target)
static inline struct arm720t_common *target_to_arm720(struct target *target)
{
return container_of(target->arch_info, struct arm720t_common,
arm7_9_common.arm);
return container_of(target->arch_info, struct arm720t_common, arm7_9_common.arm);
}

#endif /* ARM720T_H */

+ 569
- 735
src/target/arm7_9_common.c
File diff suppressed because it is too large
View File


+ 44
- 24
src/target/arm7_9_common.h View File

@@ -26,6 +26,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifndef ARM7_9_COMMON_H
#define ARM7_9_COMMON_H

@@ -37,8 +38,7 @@
/**
* Structure for items that are common between both ARM7 and ARM9 targets.
*/
struct arm7_9_common
{
struct arm7_9_common {
struct arm arm;
uint32_t common_magic;

@@ -71,16 +71,26 @@ struct arm7_9_common

struct working_area *dcc_working_area;

int (*examine_debug_reason)(struct target *target); /**< Function for determining why debug state was entered */
int (*examine_debug_reason)(struct target *target);
/**< Function for determining why debug state was entered */

void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc);
/**< Function for changing from Thumb to ARM mode */

void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]);
/**< Function for reading the core registers */

void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask,
void *buffer, int size);
void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr);
/**< Function for reading CPSR or SPSR */

void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size);
void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr);
/**< Function for writing to CPSR or SPSR */

void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr);
/**< Function for writing an immediate value to CPSR or SPSR */

void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);

void (*load_word_regs)(struct target *target, uint32_t mask);
@@ -91,25 +101,28 @@ struct arm7_9_common
void (*store_hword_reg)(struct target *target, int num);
void (*store_byte_reg)(struct target *target, int num);

void (*write_pc)(struct target *target, uint32_t pc); /**< Function for writing to the program counter */
void (*write_pc)(struct target *target, uint32_t pc);
/**< Function for writing to the program counter */

void (*branch_resume)(struct target *target);
void (*branch_resume_thumb)(struct target *target);

void (*enable_single_step)(struct target *target, uint32_t next_pc);
void (*disable_single_step)(struct target *target);

void (*set_special_dbgrq)(struct target *target); /**< Function for setting DBGRQ if the normal way won't work */
void (*set_special_dbgrq)(struct target *target);
/**< Function for setting DBGRQ if the normal way won't work */

int (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */
int (*post_debug_entry)(struct target *target);
/**< Callback function called after entering debug mode */

void (*pre_restore_context)(struct target *target); /**< Callback function called before restoring the processor context */
void (*pre_restore_context)(struct target *target);
/**< Callback function called before restoring the processor context */
};

static inline struct arm7_9_common *
target_to_arm7_9(struct target *target)
static inline struct arm7_9_common *target_to_arm7_9(struct target *target)
{
return container_of(target->arch_info, struct arm7_9_common,
arm);
return container_of(target->arch_info, struct arm7_9_common, arm);
}

static inline bool is_arm7_9(struct arm7_9_common *arm7_9)
@@ -131,13 +144,20 @@ int arm7_9_soft_reset_halt(struct target *target);
int arm7_9_prepare_reset_halt(struct target *target);

int arm7_9_halt(struct target *target);
int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer);

int arm7_9_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
int arm7_9_resume(struct target *target, int current, uint32_t address,
int handle_breakpoints, int debug_execution);
int arm7_9_step(struct target *target, int current, uint32_t address,
int handle_breakpoints);
int arm7_9_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer);
int arm7_9_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer);
int arm7_9_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, const uint8_t *buffer);

int arm7_9_run_algorithm(struct target *target, int num_mem_params,
struct mem_param *mem_params, int num_reg_prams,
struct reg_param *reg_param, uint32_t entry_point, void *arch_info);

int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);


+ 35
- 58
src/target/arm7tdmi.c View File

@@ -23,6 +23,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -32,7 +33,6 @@
#include "register.h"
#include "arm_opcodes.h"


/*
* For information about ARM7TDMI, see ARM DDI 0210C (r4p1)
* or ARM DDI 0029G (r3). "Debug In Depth", Appendix B,
@@ -50,8 +50,7 @@ static int arm7tdmi_examine_debug_reason(struct target *target)

/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
&& (target->debug_reason != DBG_REASON_SINGLESTEP)) {
struct scan_field fields[2];
uint8_t databus[4];
uint8_t breakpoint;
@@ -64,19 +63,17 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
fields[1].out_value = NULL;
fields[1].in_value = databus;

if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
{
retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;

jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

fields[0].in_value = NULL;
fields[0].out_value = &breakpoint;
@@ -96,9 +93,9 @@ static int arm7tdmi_examine_debug_reason(struct target *target)

static const int arm7tdmi_num_bits[] = {1, 32};

static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint)
static inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint)
{
uint32_t values[2]={breakpoint, flip_u32(out, 32)};
uint32_t values[2] = {breakpoint, flip_u32(out, 32)};

jtag_add_dr_out(jtag_info->tap,
2,
@@ -116,7 +113,7 @@ static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_
*
* FIXME remove the unused "deprecated" parameter
*/
static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
static inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
uint32_t out, uint32_t *deprecated, int breakpoint)
{
int retval;
@@ -136,10 +133,9 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
int retval = ERROR_OK;
struct scan_field fields[2];

if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;
@@ -159,7 +155,8 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
jtag_add_runtest(0, TAP_DRPAUSE);

#ifdef _DEBUG_INSTRUCTION_EXECUTION_
if ((retval = jtag_execute_queue()) != ERROR_OK)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;

if (in)
@@ -176,28 +173,21 @@ void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
uint32_t readback = le_to_h_u32(tmp);
if (flip)
readback = flip_u32(readback, 32);
switch (size)
{
switch (size) {
case 4:
if (be)
{
h_u32_to_be(((uint8_t*)in), readback);
} else
{
h_u32_to_le(((uint8_t*)in), readback);
}
h_u32_to_be(((uint8_t *)in), readback);
else
h_u32_to_le(((uint8_t *)in), readback);
break;
case 2:
if (be)
{
h_u16_to_be(((uint8_t*)in), readback & 0xffff);
} else
{
h_u16_to_le(((uint8_t*)in), readback & 0xffff);
}
h_u16_to_be(((uint8_t *)in), readback & 0xffff);
else
h_u16_to_le(((uint8_t *)in), readback & 0xffff);
break;
case 1:
*((uint8_t *)in)= readback & 0xff;
*((uint8_t *)in) = readback & 0xff;
break;
}
}
@@ -222,10 +212,9 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
int retval = ERROR_OK;
struct scan_field fields[2];

if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
if (retval != ERROR_OK)
return retval;
@@ -250,19 +239,14 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,

#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

if (in)
{
LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
}
LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in);
else
{
LOG_ERROR("BUG: called with in == NULL");
}
}
#endif

@@ -318,7 +302,6 @@ static void arm7tdmi_change_to_arm(struct target *target,
*pc -= 0xa;
}


/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
* roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
*
@@ -326,7 +309,7 @@ static void arm7tdmi_change_to_arm(struct target *target,
* and convert data afterwards.
*/
static void arm7tdmi_read_core_regs(struct target *target,
uint32_t mask, uint32_t* core_regs[16])
uint32_t mask, uint32_t *core_regs[16])
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -342,8 +325,7 @@ static void arm7tdmi_read_core_regs(struct target *target,
/* fetch NOP, STM in EXECUTE stage (1st cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);

for (i = 0; i <= 15; i++)
{
for (i = 0; i <= 15; i++) {
if (mask & (1 << i))
/* nothing fetched, STM still in EXECUTE (1 + i cycle) */
arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
@@ -351,7 +333,7 @@ static void arm7tdmi_read_core_regs(struct target *target,
}

static void arm7tdmi_read_core_regs_target_buffer(struct target *target,
uint32_t mask, void* buffer, int size)
uint32_t mask, void *buffer, int size)
{
int i;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -371,13 +353,10 @@ static void arm7tdmi_read_core_regs_target_buffer(struct target *target,
/* fetch NOP, STM in EXECUTE stage (1st cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);

for (i = 0; i <= 15; i++)
{
for (i = 0; i <= 15; i++) {
/* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
if (mask & (1 << i))
{
switch (size)
{
if (mask & (1 << i)) {
switch (size) {
case 4:
arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
break;
@@ -474,8 +453,7 @@ static void arm7tdmi_write_core_regs(struct target *target,
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);

for (i = 0; i <= 15; i++)
{
for (i = 0; i <= 15; i++) {
if (mask & (1 << i))
/* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
@@ -711,7 +689,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
{
struct arm7_9_common *arm7_9;

arm7_9 = calloc(1,sizeof(struct arm7_9_common));
arm7_9 = calloc(1, sizeof(struct arm7_9_common));
arm7tdmi_init_arch_info(target, arm7_9, target->tap);
arm7_9->arm.is_armv4 = true;

@@ -719,8 +697,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
}

/** Holds methods for ARM7TDMI targets. */
struct target_type arm7tdmi_target =
{
struct target_type arm7tdmi_target = {
.name = "arm7tdmi",

.poll = arm7_9_poll,


+ 1
- 0
src/target/arm7tdmi.h View File

@@ -20,6 +20,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifndef ARM7TDMI_H
#define ARM7TDMI_H



+ 222
- 303
src/target/arm920t.c
File diff suppressed because it is too large
View File


+ 6
- 10
src/target/arm920t.h View File

@@ -17,6 +17,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifndef ARM920T_H
#define ARM920T_H

@@ -25,8 +26,7 @@

#define ARM920T_COMMON_MAGIC 0xa920a920

struct arm920t_common
{
struct arm920t_common {
struct arm7_9_common arm7_9_common;
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
@@ -38,21 +38,17 @@ struct arm920t_common
int preserve_cache;
};

static inline struct arm920t_common *
target_to_arm920(struct target *target)
static inline struct arm920t_common *target_to_arm920(struct target *target)
{
return container_of(target->arch_info, struct arm920t_common,
arm7_9_common.arm);
return container_of(target->arch_info, struct arm920t_common, arm7_9_common.arm);
}

struct arm920t_cache_line
{
struct arm920t_cache_line {
uint32_t cam;
uint32_t data[8];
};

struct arm920t_tlb_entry
{
struct arm920t_tlb_entry {
uint32_t cam;
uint32_t ram1;
uint32_t ram2;


+ 44
- 78
src/target/arm926ejs.c View File

@@ -20,6 +20,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -63,10 +64,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2

buf_set_u32(address_buf, 0, 14, address);

if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
@@ -91,8 +91,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2

long long then = timeval_ms();

for (;;)
{
for (;;) {
/* rescan with NOP, to wait for the access to complete */
access_t = 0;
nr_w_buf = 0;
@@ -100,19 +99,15 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2

jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);

if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

if (buf_get_u32(&access_t, 0, 1) == 1)
{
break;
}

/* 10ms timeout */
if ((timeval_ms()-then)>10)
{
if ((timeval_ms()-then) > 10) {
LOG_ERROR("cp15 read operation timed out");
return ERROR_FAIL;
}
@@ -155,10 +150,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
buf_set_u32(address_buf, 0, 14, address);
buf_set_u32(value_buf, 0, 32, value);

if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
@@ -183,25 +177,20 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op

long long then = timeval_ms();

for (;;)
{
for (;;) {
/* rescan with NOP, to wait for the access to complete */
access_t = 0;
nr_w_buf = 0;
jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

if (buf_get_u32(&access_t, 0, 1) == 1)
{
break;
}

/* 10ms timeout */
if ((timeval_ms()-then)>10)
{
if ((timeval_ms()-then) > 10) {
LOG_ERROR("cp15 write operation timed out");
return ERROR_FAIL;
}
@@ -236,14 +225,14 @@ static int arm926ejs_examine_debug_reason(struct target *target)
int retval;

embeddedice_read_reg(dbg_stat);
if ((retval = jtag_execute_queue()) != ERROR_OK)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;

/* Method-Of-Entry (MOE) field */
debug_reason = buf_get_u32(dbg_stat->value, 6, 4);

switch (debug_reason)
{
switch (debug_reason) {
case 0:
LOG_DEBUG("no *NEW* debug entry (?missed one?)");
/* ... since last restart or debug reset ... */
@@ -337,7 +326,8 @@ static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
int retval;
uint32_t ttb = 0x0;

if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb);
if (retval != ERROR_OK)
return retval;

*result = ttb;
@@ -360,8 +350,7 @@ static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
if (retval != ERROR_OK)
return retval;

if (mmu)
{
if (mmu) {
/* invalidate TLB */
retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
if (retval != ERROR_OK)
@@ -370,8 +359,7 @@ static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
cp15_control &= ~0x1U;
}

if (d_u_cache)
{
if (d_u_cache) {
uint32_t debug_override;
/* read-modify-write CP15 debug override register
* to enable "test and clean all" */
@@ -398,8 +386,7 @@ static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
cp15_control &= ~0x4U;
}

if (i_cache)
{
if (i_cache) {
/* invalidate ICache */
retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
if (retval != ERROR_OK)
@@ -454,8 +441,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);

if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) {
uint32_t cache_type_reg;
/* identify caches */
retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
@@ -530,15 +516,13 @@ static int arm926ejs_verify_pointer(struct command_context *cmd_ctx,
/** Logs summary of ARM926 state for a halted target. */
int arm926ejs_arch_state(struct target *target)
{
static const char *state[] =
{
static const char *state[] = {
"disabled", "enabled"
};

struct arm926ejs_common *arm926ejs = target_to_arm926(target);

if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
{
if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) {
LOG_ERROR("BUG: %s", arm926_not);
return ERROR_TARGET_INVALID;
}
@@ -560,37 +544,27 @@ int arm926ejs_soft_reset_halt(struct target *target)
struct arm *arm = &arm7_9->arm;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];

if ((retval = target_halt(target)) != ERROR_OK)
{
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
}

long long then = timeval_ms();
int timeout;
while (!(timeout = ((timeval_ms()-then) > 1000)))
{
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
while (!(timeout = ((timeval_ms()-then) > 1000))) {
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
embeddedice_read_reg(dbg_stat);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}
} else
{
} else
break;
}
if (debug_level >= 1)
{
if (debug_level >= 1) {
/* do not eat all CPU, time out after 1 se*/
alive_sleep(100);
} else
{
keep_alive();
}
}
if (timeout)
{
if (timeout) {
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
@@ -636,13 +610,11 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
* Also it should be moved to the callbacks that handle breakpoints
* specifically and not the generic memory write fn's. See XScale code.
**/
if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
{
if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size == 2) || (size == 4))) {
/* special case the handling of single word writes to bypass MMU
* to allow implementation of breakpoints in memory marked read only
* by MMU */
if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
/* flush and invalidate data cache
*
* MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
@@ -662,24 +634,20 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
if (retval != ERROR_OK)
return retval;
} else
{
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
} else {
retval = arm7_9_write_memory(target, address, size, count, buffer);
if (retval != ERROR_OK)
return retval;
}

/* If ICache is enabled, we have to invalidate affected ICache lines
* the DCache is forced to write-through, so we don't have to clean it here
*/
if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{
if (count <= 1)
{
if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled) {
if (count <= 1) {
/* invalidate ICache single entry with MVA */
arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
}
else
{
} else {
/* invalidate ICache */
arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
}
@@ -748,7 +716,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm

static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
{
struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common));

/* ARM9EJ-S core always reports 0x1 in Capture-IR */
target->tap->ir_capture_mask = 0x0f;
@@ -787,8 +755,7 @@ static int arm926ejs_mmu(struct target *target, int *enabled)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);

if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_INVALID;
}
@@ -822,8 +789,7 @@ const struct command_registration arm926ejs_command_handlers[] = {
};

/** Holds methods for ARM926 targets. */
struct target_type arm926ejs_target =
{
struct target_type arm926ejs_target = {
.name = "arm926ejs",

.poll = arm7_9_poll,


+ 8
- 9
src/target/arm926ejs.h View File

@@ -17,6 +17,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifndef ARM926EJS_H
#define ARM926EJS_H

@@ -25,27 +26,25 @@

#define ARM926EJS_COMMON_MAGIC 0xa926a926

struct arm926ejs_common
{
struct arm926ejs_common {
struct arm7_9_common arm7_9_common;
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
int (*write_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value);
int (*write_cp15)(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value);
uint32_t cp15_control_reg;
uint32_t d_fsr;
uint32_t i_fsr;
uint32_t d_far;
};

static inline struct arm926ejs_common *
target_to_arm926(struct target *target)
static inline struct arm926ejs_common *target_to_arm926(struct target *target)
{
return container_of(target->arch_info, struct arm926ejs_common,
arm7_9_common.arm);
return container_of(target->arch_info, struct arm926ejs_common, arm7_9_common.arm);
}


int arm926ejs_init_arch_info(struct target *target,
struct arm926ejs_common *arm926ejs, struct jtag_tap *tap);
int arm926ejs_arch_state(struct target *target);


+ 87
- 136
src/target/arm946e.c View File

@@ -23,6 +23,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -39,8 +40,8 @@

#define NB_CACHE_WAYS 4

static uint32_t dc = 0x0;
static uint32_t ic = 0x0;
static uint32_t dc;
static uint32_t ic;

/**
* flag to give info about cache manipulation during debug :
@@ -55,8 +56,9 @@ int arm946e_post_debug_entry(struct target *target);
void arm946e_pre_restore_context(struct target *target);
static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value);


int arm946e_init_arch_info(struct target *target, struct arm946e_common *arm946e, struct jtag_tap *tap)
int arm946e_init_arch_info(struct target *target,
struct arm946e_common *arm946e,
struct jtag_tap *tap)
{
struct arm7_9_common *arm7_9 = &arm946e->arm7_9_common;

@@ -84,14 +86,14 @@ int arm946e_init_arch_info(struct target *target, struct arm946e_common *arm946e
arm946e_preserve_cache = 0;

/* override hw single-step capability from ARM9TDMI */
//arm7_9->has_single_step = 1;
/* arm7_9->has_single_step = 1; */

return ERROR_OK;
}

static int arm946e_target_create(struct target *target, Jim_Interp *interp)
{
struct arm946e_common *arm946e = calloc(1,sizeof(struct arm946e_common));
struct arm946e_common *arm946e = calloc(1, sizeof(struct arm946e_common));

arm946e_init_arch_info(target, arm946e, target->tap);

@@ -99,7 +101,7 @@ static int arm946e_target_create(struct target *target, Jim_Interp *interp)
}

static int arm946e_verify_pointer(struct command_context *cmd_ctx,
struct arm946e_common *arm946e)
struct arm946e_common *arm946e)
{
if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
command_print(cmd_ctx, "target is not an ARM946");
@@ -123,10 +125,9 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;

if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
@@ -157,10 +158,9 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
#endif

if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

return ERROR_OK;
}
@@ -177,10 +177,9 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)

buf_set_u32(value_buf, 0, 32, value);

if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
@@ -203,10 +202,9 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
#endif

if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}

return ERROR_OK;
}
@@ -214,21 +212,21 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
uint32_t arm946e_invalidate_whole_dcache(struct target *target)
{

uint32_t csize = 0;
uint32_t shift = 0;
uint32_t cp15_idx, seg, dtag;
int nb_idx, idx = 0;
int retval;
uint32_t csize = 0;
uint32_t shift = 0;
uint32_t cp15_idx, seg, dtag;
int nb_idx, idx = 0;
int retval;

/* Get cache type */
arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);
/* Get cache type */
arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);

csize = (csize >> 18) & 0x0F;
csize = (csize >> 18) & 0x0F;

if (csize == 0)
shift = 0;
else
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */

/* Cache size, given in bytes */
csize = 1 << (12 + shift);
@@ -236,16 +234,13 @@ uint32_t arm946e_invalidate_whole_dcache(struct target *target)
nb_idx = (csize / 32); /* gives nb of lines (indexes) in the cache */

/* Loop for all segmentde (i.e. ways) */
for( seg=0; seg < NB_CACHE_WAYS; seg++)
{
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
/* Loop for all indexes */
for(idx=0; idx < nb_idx; idx++)
{
for (idx = 0; idx < nb_idx; idx++) {
/* Form and write cp15 index (segment + line idx) */
cp15_idx = seg << 30 | idx << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
@@ -254,21 +249,19 @@ uint32_t arm946e_invalidate_whole_dcache(struct target *target)
arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);

/* Check cache line VALID bit */
if ( !(dtag >> 4 & 0x1) )
if (!(dtag >> 4 & 0x1))
continue;

/* Clean data cache line */
retval = arm946e_write_cp15(target, 0x35, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR cleaning cache line");
return retval;
}

/* Flush data cache line */
retval = arm946e_write_cp15(target, 0x1a, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing cache line");
return retval;
}
@@ -289,8 +282,7 @@ uint32_t arm946e_invalidate_whole_icache(struct target *target)
* mcr 15, 0, r0, cr7, cr5, {0}
*/
retval = arm946e_write_cp15(target, 0x0f, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing I$");
return retval;
}
@@ -309,10 +301,8 @@ int arm946e_post_debug_entry(struct target *target)
dc = (ctr_reg >> 2) & 0x01;
ic = (ctr_reg >> 12) & 0x01;

if (arm946e_preserve_cache)
{
if (dc == 1)
{
if (arm946e_preserve_cache) {
if (dc == 1) {
/* Clean and flush D$ */
arm946e_invalidate_whole_dcache(target);

@@ -320,8 +310,7 @@ int arm946e_post_debug_entry(struct target *target)
ctr_reg &= ~(1 << 2);
}

if (ic == 1)
{
if (ic == 1) {
/* Flush I$ */
arm946e_invalidate_whole_icache(target);

@@ -331,12 +320,11 @@ int arm946e_post_debug_entry(struct target *target)

/* Write the new configuration */
retval = arm946e_write_cp15(target, 0x02, ctr_reg);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR disabling cache");
return retval;
}
} /* if preserve_cache */
} /* if preserve_cache */

return ERROR_OK;
}
@@ -346,8 +334,7 @@ void arm946e_pre_restore_context(struct target *target)
uint32_t ctr_reg = 0x0;
uint32_t retval;

if (arm946e_preserve_cache)
{
if (arm946e_preserve_cache) {
/* Get the contents of the CTR reg */
arm946e_read_cp15(target, 0x02, (uint32_t *) &ctr_reg);

@@ -355,14 +342,12 @@ void arm946e_pre_restore_context(struct target *target)
* Read-modify-write CP15 test state register
* to reenable I/D-cache linefills
*/
if (dc == 1)
{
if (dc == 1) {
/* Enable D$ */
ctr_reg |= 1 << 2;
}

if (ic == 1)
{
if (ic == 1) {
/* Enable I$ */
ctr_reg |= 1 << 12;
}
@@ -370,14 +355,12 @@ void arm946e_pre_restore_context(struct target *target)
/* Write the new configuration */
retval = arm946e_write_cp15(target, 0x02, ctr_reg);
if (retval != ERROR_OK)
{
LOG_DEBUG("ERROR enabling cache");
}
} /* if preserve_cache */
} /* if preserve_cache */
}

uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
uint32_t size, uint32_t count)
{
uint32_t csize = 0x0;
uint32_t shift = 0;
@@ -386,8 +369,7 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
uint32_t i = 0;
int retval;

for(i = 0; i < count*size; i++)
{
for (i = 0; i < count*size; i++) {
cur_addr = address + i;

/* Get cache type */
@@ -399,14 +381,13 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
if (csize == 0)
shift = 0;
else
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */

csize = 1 << (12 + shift);

set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */

for (way = 0; way < NB_CACHE_WAYS; way++)
{
for (way = 0; way < NB_CACHE_WAYS; way++) {
/**
* Find if the affected address is kept in the cache.
* Because JTAG Scan Chain 15 offers limited approach,
@@ -417,8 +398,7 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
/* Form and write cp15 index (segment + line idx) */
cp15_idx = way << 30 | set << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
@@ -427,57 +407,51 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);

/* Check cache line VALID bit */
if ( !(dtag >> 4 & 0x1) )
if (!(dtag >> 4 & 0x1))
continue;

/* If line is valid and corresponds to affected address - invalidate it */
if (dtag >> 5 == cur_addr >> 5)
{
if (dtag >> 5 == cur_addr >> 5) {
/* Clean data cache line */
retval = arm946e_write_cp15(target, 0x35, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR cleaning cache line");
return retval;
}

/* Flush data cache line */
retval = arm946e_write_cp15(target, 0x1c, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing cache line");
return retval;
}

break;
}
} /* loop through all 4 ways */
} /* loop through all addresses */
} /* loop through all 4 ways */
} /* loop through all addresses */

return ERROR_OK;
}

uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
uint32_t size, uint32_t count)
{
uint32_t cur_addr = 0x0;
uint32_t cp15_idx, set, way, itag;
uint32_t i = 0;
int retval;

for(i = 0; i < count*size; i++)
{
for (i = 0; i < count*size; i++) {
cur_addr = address + i;

set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */

for (way = 0; way < NB_CACHE_WAYS; way++)
{
for (way = 0; way < NB_CACHE_WAYS; way++) {
/* Form and write cp15 index (segment + line idx) */
cp15_idx = way << 30 | set << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
@@ -486,31 +460,29 @@ uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
arm946e_read_cp15(target, 0x17, (uint32_t *) &itag);

/* Check cache line VALID bit */
if ( !(itag >> 4 & 0x1) )
if (!(itag >> 4 & 0x1))
continue;

/* If line is valid and corresponds to affected address - invalidate it */
if (itag >> 5 == cur_addr >> 5)
{
if (itag >> 5 == cur_addr >> 5) {
/* Flush I$ line */
retval = arm946e_write_cp15(target, 0x1d, 0x0);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing cache line");
return retval;
}