Browse Source

flash: rename CamelCase symbols

Each driver is almost self-contained, with no cross dependency.
Changing symbol names in one drive does not impact the other.

Change-Id: Ic09f844f922a35cf0a9dc23fcd61d035b38308b3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6299
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
jim
Antonio Borneo 2 years ago
parent
commit
3d135a5c70
20 changed files with 1180 additions and 1180 deletions
  1. +15
    -15
      src/flash/nand/at91sam9.c
  2. +32
    -32
      src/flash/nand/lpc32xx.c
  3. +3
    -3
      src/flash/nand/lpc32xx.h
  4. +10
    -10
      src/flash/nand/s3c24xx_regs.h
  5. +19
    -19
      src/flash/nor/aduc702x.c
  6. +17
    -17
      src/flash/nor/ambiqmicro.c
  7. +440
    -440
      src/flash/nor/at91sam3.c
  8. +439
    -439
      src/flash/nor/at91sam4.c
  9. +27
    -27
      src/flash/nor/avrf.c
  10. +3
    -3
      src/flash/nor/core.c
  11. +4
    -4
      src/flash/nor/faux.c
  12. +53
    -53
      src/flash/nor/fm3.c
  13. +39
    -39
      src/flash/nor/kinetis.c
  14. +5
    -5
      src/flash/nor/lpc2000.c
  15. +4
    -4
      src/flash/nor/numicro.c
  16. +25
    -25
      src/flash/nor/pic32mx.c
  17. +11
    -11
      src/flash/nor/psoc5lp.c
  18. +7
    -7
      src/flash/nor/stellaris.c
  19. +9
    -9
      src/flash/nor/str7x.c
  20. +18
    -18
      src/flash/nor/tms470.c

+ 15
- 15
src/flash/nand/at91sam9.c View File

@@ -25,13 +25,13 @@
#include "imp.h"
#include "arm_io.h"

#define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
#define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
#define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
#define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
#define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
#define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
#define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
#define AT91C_PIOX_SODR (0x30) /**< Offset to PIO SODR. */
#define AT91C_PIOX_CODR (0x34) /**< Offset to PIO CODR. */
#define AT91C_PIOX_PDSR (0x3C) /**< Offset to PIO PDSR. */
#define AT91C_ECCX_CR (0x00) /**< Offset to ECC CR. */
#define AT91C_ECCX_SR (0x08) /**< Offset to ECC SR. */
#define AT91C_ECCX_PR (0x0C) /**< Offset to ECC PR. */
#define AT91C_ECCX_NPR (0x10) /**< Offset to ECC NPR. */

/**
* Representation of a pin on an AT91SAM9 chip.
@@ -113,7 +113,7 @@ static int at91sam9_enable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;

return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
return target_write_u32(target, info->ce.pioc + AT91C_PIOX_CODR, 1 << info->ce.num);
}

/**
@@ -127,7 +127,7 @@ static int at91sam9_disable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;

return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
return target_write_u32(target, info->ce.pioc + AT91C_PIOX_SODR, 1 << info->ce.num);
}

/**
@@ -237,7 +237,7 @@ static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
return 0;

do {
target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
target_read_u32(target, info->busy.pioc + AT91C_PIOX_PDSR, &status);

if (status & (1 << info->busy.num))
return 1;
@@ -311,7 +311,7 @@ static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
}

/* reset ECC parity registers */
return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
return target_write_u32(target, info->ecc + AT91C_ECCX_CR, 1);
}

/**
@@ -384,7 +384,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
oob_data = at91sam9_oob_init(nand, oob, &oob_size);
retval = nand_read_data_page(nand, oob_data, oob_size);
if (ERROR_OK == retval && data) {
target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
if (status & 1) {
LOG_ERROR("Error detected!");
if (status & 4)
@@ -394,7 +394,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
uint32_t parity;

target_read_u32(target,
info->ecc + AT91C_ECCx_PR,
info->ecc + AT91C_ECCX_PR,
&parity);
uint32_t word = (parity & 0x0000FFF0) >> 4;
uint32_t bit = parity & 0x0F;
@@ -462,8 +462,8 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page,

if (!oob) {
/* no OOB given, so read in the ECC parity from the ECC controller */
target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
target_read_u32(target, info->ecc + AT91C_ECCX_PR, &parity);
target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);

oob_data[0] = (uint8_t) parity;
oob_data[1] = (uint8_t) (parity >> 8);


+ 32
- 32
src/flash/nand/lpc32xx.c View File

@@ -90,7 +90,7 @@ NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
"1000 and 20000 kHz, was %i",
lpc32xx_info->osc_freq);

lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
lpc32xx_info->selected_controller = LPC32XX_NO_CONTROLLER;
lpc32xx_info->sw_write_protection = 0;
lpc32xx_info->sw_wp_lower_bound = 0x0;
lpc32xx_info->sw_wp_upper_bound = 0x0;
@@ -222,13 +222,13 @@ static int lpc32xx_init(struct nand_device *nand)
}

/* select MLC controller if none is currently selected */
if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
"using default 'slc'");
lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
lpc32xx_info->selected_controller = LPC32XX_SLC_CONTROLLER;
}

if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint32_t mlc_icr_value = 0x0;
float cycle;
int twp, twh, trp, treh, trhz, trbwb, tcea;
@@ -304,7 +304,7 @@ static int lpc32xx_init(struct nand_device *nand)
retval = lpc32xx_reset(nand);
if (ERROR_OK != retval)
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
float cycle;
int r_setup, r_hold, r_width, r_rdy;
int w_setup, w_hold, w_width, w_rdy;
@@ -401,10 +401,10 @@ static int lpc32xx_reset(struct nand_device *nand)
return ERROR_NAND_OPERATION_FAILED;
}

if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = 0xff (reset controller and NAND device) */
retval = target_write_u32(target, 0x200b8000, 0xff);
if (ERROR_OK != retval) {
@@ -417,7 +417,7 @@ static int lpc32xx_reset(struct nand_device *nand)
"after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
retval = target_write_u32(target, 0x20020010, 0x6);
if (ERROR_OK != retval) {
@@ -447,17 +447,17 @@ static int lpc32xx_command(struct nand_device *nand, uint8_t command)
return ERROR_NAND_OPERATION_FAILED;
}

if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = command */
retval = target_write_u32(target, 0x200b8000, command);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CMD = command */
retval = target_write_u32(target, 0x20020008, command);
if (ERROR_OK != retval) {
@@ -481,17 +481,17 @@ static int lpc32xx_address(struct nand_device *nand, uint8_t address)
return ERROR_NAND_OPERATION_FAILED;
}

if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_ADDR = address */
retval = target_write_u32(target, 0x200b8004, address);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_ADDR = address */
retval = target_write_u32(target, 0x20020004, address);
if (ERROR_OK != retval) {
@@ -515,17 +515,17 @@ static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
return ERROR_NAND_OPERATION_FAILED;
}

if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_DATA = data */
retval = target_write_u32(target, 0x200b0000, data);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_DATA = data */
retval = target_write_u32(target, 0x20020000, data);
if (ERROR_OK != retval) {
@@ -549,10 +549,10 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
return ERROR_NAND_OPERATION_FAILED;
}

if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* data = MLC_DATA, use sized access */
if (nand->bus_width == 8) {
uint8_t *data8 = data;
@@ -565,7 +565,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
LOG_ERROR("could not read MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t data32;

/* data = SLC_DATA, must use 32-bit access */
@@ -1233,10 +1233,10 @@ static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
return ERROR_NAND_OPERATION_FAILED;
}

if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (!data && oob) {
LOG_ERROR("LPC32xx MLC controller can't write "
"OOB data only");
@@ -1256,7 +1256,7 @@ static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,

retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
oob, oob_size);
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
if (!data && oob) {
/*
@@ -1584,17 +1584,17 @@ static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
return ERROR_NAND_OPERATION_FAILED;
}

if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (data_size > (uint32_t)nand->page_size) {
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
oob, oob_size);
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;

retval = target_alloc_working_area(target,
@@ -1628,7 +1628,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);

do {
if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status;

/* Read MLC_ISR, wait for controller to become ready */
@@ -1643,7 +1643,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
timeout);
return 1;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status;

/* Read SLC_STAT and check READY bit */
@@ -1681,7 +1681,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);

do {
if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status = 0x0;

/* Read MLC_ISR, wait for NAND flash device to
@@ -1697,7 +1697,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
timeout);
return 1;
}
} else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status = 0x0;

/* Read SLC_STAT and check READY bit */
@@ -1770,10 +1770,10 @@ COMMAND_HANDLER(handle_lpc32xx_select_command)
if (CMD_ARGC >= 2) {
if (strcmp(CMD_ARGV[1], "mlc") == 0) {
lpc32xx_info->selected_controller =
LPC32xx_MLC_CONTROLLER;
LPC32XX_MLC_CONTROLLER;
} else if (strcmp(CMD_ARGV[1], "slc") == 0) {
lpc32xx_info->selected_controller =
LPC32xx_SLC_CONTROLLER;
LPC32XX_SLC_CONTROLLER;
} else
return ERROR_COMMAND_SYNTAX_ERROR;
}


+ 3
- 3
src/flash/nand/lpc32xx.h View File

@@ -20,9 +20,9 @@
#define OPENOCD_FLASH_NAND_LPC32XX_H

enum lpc32xx_selected_controller {
LPC32xx_NO_CONTROLLER,
LPC32xx_MLC_CONTROLLER,
LPC32xx_SLC_CONTROLLER,
LPC32XX_NO_CONTROLLER,
LPC32XX_MLC_CONTROLLER,
LPC32XX_SLC_CONTROLLER,
};

struct lpc32xx_nand_controller {


+ 10
- 10
src/flash/nand/s3c24xx_regs.h View File

@@ -61,7 +61,7 @@
#define S3C2410_NFCONF_512BYTE (1 << 14)
#define S3C2410_NFCONF_4STEP (1 << 13)
#define S3C2410_NFCONF_INITECC (1 << 12)
#define S3C2410_NFCONF_nFCE (1 << 11)
#define S3C2410_NFCONF_NFCE (1 << 11)
#define S3C2410_NFCONF_TACLS(x) ((x) << 8)
#define S3C2410_NFCONF_TWRPH0(x) ((x) << 4)
#define S3C2410_NFCONF_TWRPH1(x) ((x) << 0)
@@ -83,12 +83,12 @@
#define S3C2440_NFCONT_SPARE_ECCLOCK (1 << 6)
#define S3C2440_NFCONT_MAIN_ECCLOCK (1 << 5)
#define S3C2440_NFCONT_INITECC (1 << 4)
#define S3C2440_NFCONT_nFCE (1 << 1)
#define S3C2440_NFCONT_NFCE (1 << 1)
#define S3C2440_NFCONT_ENABLE (1 << 0)

#define S3C2440_NFSTAT_READY (1 << 0)
#define S3C2440_NFSTAT_nCE (1 << 1)
#define S3C2440_NFSTAT_RnB_CHANGE (1 << 2)
#define S3C2440_NFSTAT_NCE (1 << 1)
#define S3C2440_NFSTAT_RNB_CHANGE (1 << 2)
#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1 << 3)

#define S3C2412_NFCONF_NANDBOOT (1 << 31)
@@ -103,16 +103,16 @@
#define S3C2412_NFCONT_ECC4_DECINT (1 << 12)
#define S3C2412_NFCONT_MAIN_ECC_LOCK (1 << 7)
#define S3C2412_NFCONT_INIT_MAIN_ECC (1 << 5)
#define S3C2412_NFCONT_nFCE1 (1 << 2)
#define S3C2412_NFCONT_nFCE0 (1 << 1)
#define S3C2412_NFCONT_NFCE1 (1 << 2)
#define S3C2412_NFCONT_NFCE0 (1 << 1)

#define S3C2412_NFSTAT_ECC_ENCDONE (1 << 7)
#define S3C2412_NFSTAT_ECC_DECDONE (1 << 6)
#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1 << 5)
#define S3C2412_NFSTAT_RnB_CHANGE (1 << 4)
#define S3C2412_NFSTAT_nFCE1 (1 << 3)
#define S3C2412_NFSTAT_nFCE0 (1 << 2)
#define S3C2412_NFSTAT_Res1 (1 << 1)
#define S3C2412_NFSTAT_RNB_CHANGE (1 << 4)
#define S3C2412_NFSTAT_NFCE1 (1 << 3)
#define S3C2412_NFSTAT_NFCE0 (1 << 2)
#define S3C2412_NFSTAT_RES1 (1 << 1)
#define S3C2412_NFSTAT_READY (1 << 0)

#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)


+ 19
- 19
src/flash/nor/aduc702x.c View File

@@ -31,15 +31,15 @@ static int aduc702x_build_sector_list(struct flash_bank *bank);
static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms);
static int aduc702x_set_write_enable(struct target *target, int enable);

#define ADUC702x_FLASH 0xfffff800
#define ADUC702x_FLASH_FEESTA (0*4)
#define ADUC702x_FLASH_FEEMOD (1*4)
#define ADUC702x_FLASH_FEECON (2*4)
#define ADUC702x_FLASH_FEEDAT (3*4)
#define ADUC702x_FLASH_FEEADR (4*4)
#define ADUC702x_FLASH_FEESIGN (5*4)
#define ADUC702x_FLASH_FEEPRO (6*4)
#define ADUC702x_FLASH_FEEHIDE (7*4)
#define ADUC702X_FLASH 0xfffff800
#define ADUC702X_FLASH_FEESTA (0*4)
#define ADUC702X_FLASH_FEEMOD (1*4)
#define ADUC702X_FLASH_FEECON (2*4)
#define ADUC702X_FLASH_FEEDAT (3*4)
#define ADUC702X_FLASH_FEEADR (4*4)
#define ADUC702X_FLASH_FEESIGN (5*4)
#define ADUC702X_FLASH_FEEPRO (6*4)
#define ADUC702X_FLASH_FEEHIDE (7*4)

/* flash bank aduc702x 0 0 0 0 <target#>
* The ADC7019-28 devices all have the same flash layout */
@@ -87,9 +87,9 @@ static int aduc702x_erase(struct flash_bank *bank, unsigned int first,
/* mass erase */
if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
LOG_DEBUG("performing mass erase.");
target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, 0x3cff);
target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, 0xffc3);
target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x06);

if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK) {
LOG_ERROR("mass erase failed");
@@ -106,8 +106,8 @@ static int aduc702x_erase(struct flash_bank *bank, unsigned int first,
for (x = 0; x < count; ++x) {
adr = bank->base + ((first + x) * 512);

target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, adr);
target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x05);

if (aduc702x_check_flash_completion(target, 50) != ERROR_OK) {
LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
@@ -283,7 +283,7 @@ static int aduc702x_write_single(struct flash_bank *bank,

for (x = 0; x < count; x += 2) {
/* FEEADR = address */
target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, offset + x);

/* set up data */
if ((x + 1) == count) {
@@ -292,10 +292,10 @@ static int aduc702x_write_single(struct flash_bank *bank,
} else
b = buffer[x + 1];

target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, buffer[x] | (b << 8));

/* do single-write command */
target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x02);

if (aduc702x_check_flash_completion(target, 1) != ERROR_OK) {
LOG_ERROR("single write failed for address 0x%08lX",
@@ -345,7 +345,7 @@ static int aduc702x_probe(struct flash_bank *bank)
static int aduc702x_set_write_enable(struct target *target, int enable)
{
/* don't bother to preserve int enable bit here */
target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEMOD, enable ? 8 : 0);

return ERROR_OK;
}
@@ -361,7 +361,7 @@ static int aduc702x_check_flash_completion(struct target *target, unsigned int t

int64_t endtime = timeval_ms() + timeout_ms;
while (1) {
target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
target_read_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEESTA, &v);
if ((v & 4) == 0)
break;
alive_sleep(1);


+ 17
- 17
src/flash/nor/ambiqmicro.c View File

@@ -123,7 +123,7 @@ static struct {
uint8_t class;
uint8_t partno;
const char *partname;
} ambiqmicroParts[6] = {
} ambiqmicro_parts[6] = {
{0xFF, 0x00, "Unknown"},
{0x01, 0x00, "Apollo"},
{0x02, 0x00, "Apollo2"},
@@ -132,7 +132,7 @@ static struct {
{0x05, 0x00, "Apollo"},
};

static char *ambiqmicroClassname[6] = {
static char *ambiqmicro_classname[6] = {
"Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
};

@@ -172,10 +172,10 @@ static int get_ambiqmicro_info(struct flash_bank *bank, struct command_invocatio
}

/* Check class name in range. */
if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
classname = ambiqmicroClassname[ambiqmicro_info->target_class];
if (ambiqmicro_info->target_class < sizeof(ambiqmicro_classname))
classname = ambiqmicro_classname[ambiqmicro_info->target_class];
else
classname = ambiqmicroClassname[0];
classname = ambiqmicro_classname[0];

command_print_sameline(cmd, "\nAmbiq Micro information: Chip is "
"class %d (%s) %s\n",
@@ -195,24 +195,24 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t PartNum = 0;
uint32_t part_num = 0;
int retval;

/*
* Read Part Number.
*/
retval = target_read_u32(target, 0x40020000, &PartNum);
retval = target_read_u32(target, 0x40020000, &part_num);
if (retval != ERROR_OK) {
LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
/* Set PartNum to default device */
PartNum = 0;
LOG_ERROR("status(0x%x):Could not read part_num.\n", retval);
/* Set part_num to default device */
part_num = 0;
}
LOG_DEBUG("Part number: 0x%" PRIx32, PartNum);
LOG_DEBUG("Part number: 0x%" PRIx32, part_num);

/*
* Determine device class.
*/
ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24;

switch (ambiqmicro_info->target_class) {
case 1: /* 1 - Apollo */
@@ -220,9 +220,9 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
bank->base = bank->bank_number * 0x40000;
ambiqmicro_info->pagesize = 2048;
ambiqmicro_info->flshsiz =
apollo_flash_size[(PartNum & 0x00F00000) >> 20];
apollo_flash_size[(part_num & 0x00F00000) >> 20];
ambiqmicro_info->sramsiz =
apollo_sram_size[(PartNum & 0x000F0000) >> 16];
apollo_sram_size[(part_num & 0x000F0000) >> 16];
ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
ambiqmicro_info->pagesize;
if (ambiqmicro_info->num_pages > 128) {
@@ -248,12 +248,12 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)

}

if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicroParts))
if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts))
ambiqmicro_info->target_name =
ambiqmicroParts[ambiqmicro_info->target_class].partname;
ambiqmicro_parts[ambiqmicro_info->target_class].partname;
else
ambiqmicro_info->target_name =
ambiqmicroParts[0].partname;
ambiqmicro_parts[0].partname;

LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
ambiqmicro_info->num_pages,


+ 440
- 440
src/flash/nor/at91sam3.c
File diff suppressed because it is too large
View File


+ 439
- 439
src/flash/nor/at91sam4.c
File diff suppressed because it is too large
View File


+ 27
- 27
src/flash/nor/avrf.c View File

@@ -38,14 +38,14 @@
#define AVR_JTAG_INS_PROG_PAGEREAD 0x07

/* Data Registers: */
#define AVR_JTAG_REG_Bypass_Len 1
#define AVR_JTAG_REG_DeviceID_Len 32
#define AVR_JTAG_REG_BYPASS_LEN 1
#define AVR_JTAG_REG_DEVICEID_LEN 32

#define AVR_JTAG_REG_Reset_Len 1
#define AVR_JTAG_REG_JTAGID_Len 32
#define AVR_JTAG_REG_ProgrammingEnable_Len 16
#define AVR_JTAG_REG_ProgrammingCommand_Len 15
#define AVR_JTAG_REG_FlashDataByte_Len 16
#define AVR_JTAG_REG_RESET_LEN 1
#define AVR_JTAG_REG_JTAGID_LEN 32
#define AVR_JTAG_REG_PROGRAMMING_ENABLE_LEN 16
#define AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN 15
#define AVR_JTAG_REG_FLASH_DATA_BYTE_LEN 16

struct avrf_type {
char name[15];
@@ -81,7 +81,7 @@ static const struct avrf_type avft_chips_info[] = {
static int avr_jtag_reset(struct avr_common *avr, uint32_t reset)
{
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
avr_jtag_senddat(avr->jtag_info.tap, NULL, reset, AVR_JTAG_REG_Reset_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, reset, AVR_JTAG_REG_RESET_LEN);

return ERROR_OK;
}
@@ -89,7 +89,7 @@ static int avr_jtag_reset(struct avr_common *avr, uint32_t reset)
static int avr_jtag_read_jtagid(struct avr_common *avr, uint32_t *id)
{
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_LEN);

return ERROR_OK;
}
@@ -99,7 +99,7 @@ static int avr_jtagprg_enterprogmode(struct avr_common *avr)
avr_jtag_reset(avr, 1);

avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_PROGRAMMING_ENABLE_LEN);

return ERROR_OK;
}
@@ -107,11 +107,11 @@ static int avr_jtagprg_enterprogmode(struct avr_common *avr)
static int avr_jtagprg_leaveprogmode(struct avr_common *avr)
{
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);

avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_PROGRAMMING_ENABLE_LEN);

avr_jtag_reset(avr, 0);

@@ -123,17 +123,17 @@ static int avr_jtagprg_chiperase(struct avr_common *avr)
uint32_t poll_value;

avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);

do {
poll_value = 0;
avr_jtag_senddat(avr->jtag_info.tap,
&poll_value,
0x3380,
AVR_JTAG_REG_ProgrammingCommand_Len);
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (ERROR_OK != mcu_execute_queue())
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
@@ -152,26 +152,26 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr,
uint32_t poll_value;

avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);

/* load extended high byte */
if (ext_addressing)
avr_jtag_senddat(avr->jtag_info.tap,
NULL,
0x0b00 | ((addr >> 17) & 0xFF),
AVR_JTAG_REG_ProgrammingCommand_Len);
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);

/* load addr high byte */
avr_jtag_senddat(avr->jtag_info.tap,
NULL,
0x0700 | ((addr >> 9) & 0xFF),
AVR_JTAG_REG_ProgrammingCommand_Len);
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);

/* load addr low byte */
avr_jtag_senddat(avr->jtag_info.tap,
NULL,
0x0300 | ((addr >> 1) & 0xFF),
AVR_JTAG_REG_ProgrammingCommand_Len);
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);

avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);

@@ -184,17 +184,17 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr,

avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);

avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);

do {
poll_value = 0;
avr_jtag_senddat(avr->jtag_info.tap,
&poll_value,
0x3700,
AVR_JTAG_REG_ProgrammingCommand_Len);
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (ERROR_OK != mcu_execute_queue())
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);


+ 3
- 3
src/flash/nor/core.c View File

@@ -345,7 +345,7 @@ static int default_flash_mem_blank_check(struct flash_bank *bank)
{
struct target *target = bank->target;
const int buffer_size = 1024;
uint32_t nBytes;
uint32_t n_bytes;
int retval = ERROR_OK;

if (bank->target->state != TARGET_HALTED) {
@@ -373,8 +373,8 @@ static int default_flash_mem_blank_check(struct flash_bank *bank)
if (retval != ERROR_OK)
goto done;

for (nBytes = 0; nBytes < chunk; nBytes++) {
if (buffer[nBytes] != bank->erased_value) {
for (n_bytes = 0; n_bytes < chunk; n_bytes++) {
if (buffer[n_bytes] != bank->erased_value) {
bank->sectors[i].is_erased = 0;
break;
}


+ 4
- 4
src/flash/nor/faux.c View File

@@ -30,7 +30,7 @@ struct faux_flash_bank {
uint32_t start_address;
};

static const int sectorSize = 0x10000;
static const int sector_size = 0x10000;


/* flash bank faux <base> <size> <chip_width> <bus_width> <target#> <driverPath>
@@ -57,11 +57,11 @@ FLASH_BANK_COMMAND_HANDLER(faux_flash_bank_command)

/* Use 0x10000 as a fixed sector size. */
uint32_t offset = 0;
bank->num_sectors = bank->size/sectorSize;
bank->num_sectors = bank->size/sector_size;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
for (unsigned int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = offset;
bank->sectors[i].size = sectorSize;
bank->sectors[i].size = sector_size;
offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 0;
@@ -81,7 +81,7 @@ static int faux_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
struct faux_flash_bank *info = bank->driver_priv;
memset(info->memory + first*sectorSize, 0xff, sectorSize*(last-first + 1));
memset(info->memory + first*sector_size, 0xff, sector_size*(last-first + 1));
return ERROR_OK;
}



+ 53
- 53
src/flash/nor/fm3.c View File

@@ -207,24 +207,24 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
struct fm3_flash_bank *fm3_info = bank->driver_priv;
struct target *target = bank->target;
int retval = ERROR_OK;
uint32_t u32DummyRead;
uint32_t u32_dummy_read;
int odd;
uint32_t u32FlashType;
uint32_t u32FlashSeqAddress1;
uint32_t u32FlashSeqAddress2;
uint32_t u32_flash_type;
uint32_t u32_flash_seq_address1;
uint32_t u32_flash_seq_address2;

struct working_area *write_algorithm;
struct reg_param reg_params[3];
struct armv7m_algorithm armv7m_info;

u32FlashType = (uint32_t) fm3_info->flashtype;
u32_flash_type = (uint32_t) fm3_info->flashtype;

if (u32FlashType == fm3_flash_type1) {
u32FlashSeqAddress1 = 0x00001550;
u32FlashSeqAddress2 = 0x00000AA8;
} else if (u32FlashType == fm3_flash_type2) {
u32FlashSeqAddress1 = 0x00000AA8;
u32FlashSeqAddress2 = 0x00000554;
if (u32_flash_type == fm3_flash_type1) {
u32_flash_seq_address1 = 0x00001550;
u32_flash_seq_address2 = 0x00000AA8;
} else if (u32_flash_type == fm3_flash_type2) {
u32_flash_seq_address1 = 0x00000AA8;
u32_flash_seq_address2 = 0x00000554;
} else {
LOG_ERROR("Flash/Device type unknown!");
return ERROR_FLASH_OPERATION_FAILED;
@@ -282,7 +282,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
return retval;

/* dummy read of FASZR */
retval = target_read_u32(target, 0x40000000, &u32DummyRead);
retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
if (retval != ERROR_OK)
return retval;

@@ -300,8 +300,8 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;

init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* u32FlashSeqAddress1 */
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* u32FlashSeqAddress2 */
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */
init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* offset */

/* write code buffer and use Flash sector erase code within fm3 */
@@ -312,8 +312,8 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
if (odd)
offset += 4;

buf_set_u32(reg_params[0].value, 0, 32, u32FlashSeqAddress1);
buf_set_u32(reg_params[1].value, 0, 32, u32FlashSeqAddress2);
buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);
buf_set_u32(reg_params[2].value, 0, 32, offset);

retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
@@ -341,7 +341,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
if (retval != ERROR_OK)
return retval;

retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */

return retval;
}
@@ -358,22 +358,22 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer,
struct reg_param reg_params[6];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
uint32_t u32FlashType;
uint32_t u32FlashSeqAddress1;
uint32_t u32FlashSeqAddress2;
uint32_t u32_flash_type;
uint32_t u32_flash_seq_address1;
uint32_t u32_flash_seq_address2;

/* Increase buffer_size if needed */
if (buffer_size < (target->working_area_size / 2))
buffer_size = (target->working_area_size / 2);

u32FlashType = (uint32_t) fm3_info->flashtype;
u32_flash_type = (uint32_t) fm3_info->flashtype;

if (u32FlashType == fm3_flash_type1) {
u32FlashSeqAddress1 = 0x00001550;
u32FlashSeqAddress2 = 0x00000AA8;
} else if (u32FlashType == fm3_flash_type2) {
u32FlashSeqAddress1 = 0x00000AA8;
u32FlashSeqAddress2 = 0x00000554;
if (u32_flash_type == fm3_flash_type1) {
u32_flash_seq_address1 = 0x00001550;
u32_flash_seq_address2 = 0x00000AA8;
} else if (u32_flash_type == fm3_flash_type2) {
u32_flash_seq_address1 = 0x00000AA8;
u32_flash_seq_address2 = 0x00000554;
} else {
LOG_ERROR("Flash/Device type unknown!");
return ERROR_FLASH_OPERATION_FAILED;
@@ -401,8 +401,8 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer,
0x55, 0xF0, 0x01, 0x05, /* ORRS.W R5, R5, #1 */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x35, 0x60, /* STR R5, [R6] */
/* u32DummyRead = fm3_FLASH_IF->FASZ; */
0x28, 0x4D, /* LDR.N R5, ??u32DummyRead */
/* u32_dummy_read = fm3_FLASH_IF->FASZ; */
0x28, 0x4D, /* LDR.N R5, ??u32_dummy_read */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x36, 0x68, /* LDR R6, [R6] */
0x2E, 0x60, /* STR R6, [R5] */
@@ -492,8 +492,8 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer,
0x55, 0xF0, 0x02, 0x05, /* ORRS.W R5, R5, #2 */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x35, 0x60, /* STR R5, [R6] */
/* u32DummyRead = fm3_FLASH_IF->FASZ; */
0x04, 0x4D, /* LDR.N R5, ??u32DummyRead */
/* u32_dummy_read = fm3_FLASH_IF->FASZ; */
0x04, 0x4D, /* LDR.N R5, ??u32_dummy_read */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x36, 0x68, /* LDR R6, [R6] */
0x2E, 0x60, /* STR R6, [R5] */
@@ -508,7 +508,7 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer,
/* SRAM basic-address + 8.These address pointers will be patched, if a */
/* different start address in RAM is used (e.g. for Flash type 2)! */
/* Default SRAM basic-address is 0x20000000. */
0x00, 0x00, 0x00, 0x20, /* u32DummyRead address in RAM (0x20000000) */
0x00, 0x00, 0x00, 0x20, /* u32_dummy_read address in RAM (0x20000000) */
0x04, 0x00, 0x00, 0x20 /* u32FlashResult address in RAM (0x20000004) */
};

@@ -548,7 +548,7 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer,
return retval;

/* Patching 'local variable address' */
/* Algorithm: u32DummyRead: */
/* Algorithm: u32_dummy_read: */
retval = target_write_u32(target, (write_algorithm->address + 8)
+ sizeof(fm3_flash_write_code) - 8, (write_algorithm->address));
if (retval != ERROR_OK)
@@ -595,8 +595,8 @@ static int fm3_write_block(struct flash_bank *bank, const uint8_t *buffer,
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
buf_set_u32(reg_params[3].value, 0, 32, u32FlashSeqAddress1);
buf_set_u32(reg_params[4].value, 0, 32, u32FlashSeqAddress2);
buf_set_u32(reg_params[3].value, 0, 32, u32_flash_seq_address1);
buf_set_u32(reg_params[4].value, 0, 32, u32_flash_seq_address2);

retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
(write_algorithm->address + 8), 0, 1000, &armv7m_info);
@@ -816,25 +816,25 @@ static int fm3_chip_erase(struct flash_bank *bank)
struct target *target = bank->target;
struct fm3_flash_bank *fm3_info2 = bank->driver_priv;
int retval = ERROR_OK;
uint32_t u32DummyRead;
uint32_t u32FlashType;
uint32_t u32FlashSeqAddress1;
uint32_t u32FlashSeqAddress2;
uint32_t u32_dummy_read;
uint32_t u32_flash_type;
uint32_t u32_flash_seq_address1;
uint32_t u32_flash_seq_address2;

struct working_area *write_algorithm;
struct reg_param reg_params[3];
struct armv7m_algorithm armv7m_info;

u32FlashType = (uint32_t) fm3_info2->flashtype;
u32_flash_type = (uint32_t) fm3_info2->flashtype;

if (u32FlashType == fm3_flash_type1) {
if (u32_flash_type == fm3_flash_type1) {
LOG_INFO("*** Erasing mb9bfxxx type");
u32FlashSeqAddress1 = 0x00001550;
u32FlashSeqAddress2 = 0x00000AA8;
} else if (u32FlashType == fm3_flash_type2) {
u32_flash_seq_address1 = 0x00001550;
u32_flash_seq_address2 = 0x00000AA8;
} else if (u32_flash_type == fm3_flash_type2) {
LOG_INFO("*** Erasing mb9afxxx type");
u32FlashSeqAddress1 = 0x00000AA8;
u32FlashSeqAddress2 = 0x00000554;
u32_flash_seq_address1 = 0x00000AA8;
u32_flash_seq_address2 = 0x00000554;
} else {
LOG_ERROR("Flash/Device type unknown!");
return ERROR_FLASH_OPERATION_FAILED;
@@ -891,7 +891,7 @@ static int fm3_chip_erase(struct flash_bank *bank)
return retval;

/* dummy read of FASZR */
retval = target_read_u32(target, 0x40000000, &u32DummyRead);
retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
if (retval != ERROR_OK)
return retval;

@@ -909,11 +909,11 @@ static int fm3_chip_erase(struct flash_bank *bank)
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;

init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* u32FlashSeqAddress1 */
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* u32FlashSeqAddress2 */
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */

buf_set_u32(reg_params[0].value, 0, 32, u32FlashSeqAddress1);
buf_set_u32(reg_params[1].value, 0, 32, u32FlashSeqAddress2);
buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);

retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
write_algorithm->address, 0, 100000, &armv7m_info);
@@ -928,7 +928,7 @@ static int fm3_chip_erase(struct flash_bank *bank)
destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]);

retval = fm3_busy_wait(target, u32FlashSeqAddress2, 20000); /* 20s timeout */
retval = fm3_busy_wait(target, u32_flash_seq_address2, 20000); /* 20s timeout */
if (retval != ERROR_OK)
return retval;

@@ -937,7 +937,7 @@ static int fm3_chip_erase(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;

retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */

return retval;
}


+ 39
- 39
src/flash/nor/kinetis.c View File

@@ -91,11 +91,11 @@

#define MSCM_OCMDR0 0x40001400
#define FMC_PFB01CR 0x4001f004
#define FTFx_FSTAT 0x40020000
#define FTFx_FCNFG 0x40020001
#define FTFx_FCCOB3 0x40020004
#define FTFx_FPROT3 0x40020010
#define FTFx_FDPROT 0x40020017
#define FTFX_FSTAT 0x40020000
#define FTFX_FCNFG 0x40020001
#define FTFX_FCCOB3 0x40020004
#define FTFX_FPROT3 0x40020010
#define FTFX_FDPROT 0x40020017
#define SIM_BASE 0x40047000
#define SIM_BASE_KL28 0x40074000
#define SIM_COPC 0x40048100
@@ -124,14 +124,14 @@
#define PM_CTRL_RUNM_RUN 0x00

/* Commands */
#define FTFx_CMD_BLOCKSTAT 0x00
#define FTFx_CMD_SECTSTAT 0x01
#define FTFx_CMD_LWORDPROG 0x06
#define FTFx_CMD_SECTERASE 0x09
#define FTFx_CMD_SECTWRITE 0x0b
#define FTFx_CMD_MASSERASE 0x44
#define FTFx_CMD_PGMPART 0x80
#define FTFx_CMD_SETFLEXRAM 0x81
#define FTFX_CMD_BLOCKSTAT 0x00
#define FTFX_CMD_SECTSTAT 0x01
#define FTFX_CMD_LWORDPROG 0x06
#define FTFX_CMD_SECTERASE 0x09
#define FTFX_CMD_SECTWRITE 0x0b
#define FTFX_CMD_MASSERASE 0x44
#define FTFX_CMD_PGMPART 0x80
#define FTFX_CMD_SETFLEXRAM 0x81

/* The older Kinetis K series uses the following SDID layout :
* Bit 31-16 : 0
@@ -232,8 +232,8 @@

/* The field originally named DIEID has new name/meaning on KE1x */
#define KINETIS_SDID_PROJECTID_MASK KINETIS_SDID_DIEID_MASK
#define KINETIS_SDID_PROJECTID_KE1xF 0x00000080
#define KINETIS_SDID_PROJECTID_KE1xZ 0x00000100
#define KINETIS_SDID_PROJECTID_KE1XF 0x00000080
#define KINETIS_SDID_PROJECTID_KE1XZ 0x00000100

struct kinetis_flash_bank {
struct kinetis_chip *k_chip;
@@ -1209,7 +1209,7 @@ static int kinetis_ftfx_decode_error(uint8_t fstat)
static int kinetis_ftfx_clear_error(struct target *target)
{
/* reset error flags */
return target_write_u8(target, FTFx_FSTAT, 0x70);
return target_write_u8(target, FTFX_FSTAT, 0x70);
}


@@ -1220,7 +1220,7 @@ static int kinetis_ftfx_prepare(struct target *target)

/* wait until busy */
for (unsigned int i = 0; i < 50; i++) {
result = target_read_u8(target, FTFx_FSTAT, &fstat);
result = target_read_u8(target, FTFX_FSTAT, &fstat);
if (result != ERROR_OK)
return result;

@@ -1300,7 +1300,7 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
buf_set_u32(reg_params[1].value, 0, 32, wcount);
buf_set_u32(reg_params[2].value, 0, 32, source->address);
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
buf_set_u32(reg_params[4].value, 0, 32, FTFX_FSTAT);

retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
0, NULL,
@@ -1314,12 +1314,12 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,

LOG_ERROR("Error writing flash at %08" PRIx32, end_address);

retval = target_read_u8(target, FTFx_FSTAT, &fstat);
retval = target_read_u8(target, FTFX_FSTAT, &fstat);
if (retval == ERROR_OK) {
retval = kinetis_ftfx_decode_error(fstat);

/* reset error flags */
target_write_u8(target, FTFx_FSTAT, 0x70);
target_write_u8(target, FTFX_FSTAT, 0x70);
}
} else if (retval != ERROR_OK)
LOG_ERROR("Error executing kinetis Flash programming algorithm");
@@ -1369,7 +1369,7 @@ static int kinetis_protect_check(struct flash_bank *bank)
if (k_bank->flash_class == FC_PFLASH) {

/* read protection register */
result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
result = target_read_u32(bank->target, FTFX_FPROT3, &fprot);
if (result != ERROR_OK)
return result;

@@ -1379,7 +1379,7 @@ static int kinetis_protect_check(struct flash_bank *bank)
uint8_t fdprot;

/* read protection register */
result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
result = target_read_u8(bank->target, FTFX_FDPROT, &fdprot);
if (result != ERROR_OK)
return result;

@@ -1475,18 +1475,18 @@ static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t fa
uint8_t fstat;
int64_t ms_timeout = timeval_ms() + 250;

result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
result = target_write_memory(target, FTFX_FCCOB3, 4, 3, command);
if (result != ERROR_OK)
return result;

/* start command */
result = target_write_u8(target, FTFx_FSTAT, 0x80);
result = target_write_u8(target, FTFX_FSTAT, 0x80);
if (result != ERROR_OK)
return result;

/* wait for done */
do {
result = target_read_u8(target, FTFx_FSTAT, &fstat);
result = target_read_u8(target, FTFX_FSTAT, &fstat);

if (result != ERROR_OK)
return result;
@@ -1641,7 +1641,7 @@ static int kinetis_erase(struct flash_bank *bank, unsigned int first,
*/
for (unsigned int i = first; i <= last; i++) {
/* set command and sector address */
result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
0, 0, 0, 0, 0, 0, 0, 0, NULL);

if (result != ERROR_OK) {
@@ -1679,7 +1679,7 @@ static int kinetis_make_ram_ready(struct target *target)
uint8_t ftfx_fcnfg;

/* check if ram ready */
result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
if (result != ERROR_OK)
return result;

@@ -1687,13 +1687,13 @@ static int kinetis_make_ram_ready(struct target *target)
return ERROR_OK; /* ram ready */

/* make flex ram available */
result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
result = kinetis_ftfx_command(target, FTFX_CMD_SETFLEXRAM, 0x00ff0000,
0, 0, 0, 0, 0, 0, 0, 0, NULL);
if (result != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;

/* check again */
result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
if (result != ERROR_OK)
return result;

@@ -1766,7 +1766,7 @@ static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer
}

/* execute section-write command */
result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTWRITE,
k_bank->prog_base + offset - align_begin,
chunk_count>>8, chunk_count, 0, 0,
0, 0, 0, 0, &ftfx_fstat);
@@ -1869,7 +1869,7 @@ static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,

LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));

result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
result = kinetis_ftfx_command(bank->target, FTFX_CMD_LWORDPROG, k_bank->prog_base + offset,
buffer[3], buffer[2], buffer[1], buffer[0],
0, 0, 0, 0, &ftfx_fstat);

@@ -2405,8 +2405,8 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
switch (k_chip->sim_sdid &
(KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1XZ:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1XZ:
/* KE1xZ: FTFE, 2kB sectors */
k_chip->pflash_sector_size = 2<<10;
k_chip->nvm_sector_size = 2<<10;
@@ -2420,9 +2420,9 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
familyid, subfamid, cpu_mhz / 10);
break;

case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1XF:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1XF:
case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1XF:
/* KE1xF: FTFE, 4kB sectors */
k_chip->pflash_sector_size = 4<<10;
k_chip->nvm_sector_size = 2<<10;
@@ -2827,7 +2827,7 @@ static int kinetis_blank_check(struct flash_bank *bank)

if (use_block_cmd) {
/* check if whole bank is blank */
result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
result = kinetis_ftfx_command(bank->target, FTFX_CMD_BLOCKSTAT, k_bank->prog_base,
0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);

if (result != ERROR_OK)
@@ -2840,7 +2840,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
/* the whole bank is not erased, check sector-by-sector */
for (unsigned int i = 0; i < bank->num_sectors; i++) {
/* normal margin */
result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTSTAT,
k_bank->prog_base + bank->sectors[i].offset,
1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);

@@ -2992,7 +2992,7 @@ COMMAND_HANDLER(kinetis_nvm_partition)
if (result != ERROR_OK)
return result;

result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
result = kinetis_ftfx_command(target, FTFX_CMD_PGMPART, load_flex_ram,
ee_size_code, flex_nvm_partition_code, 0, 0,
0, 0, 0, 0, NULL);
if (result != ERROR_OK)


+ 5
- 5
src/flash/nor/lpc2000.c View File

@@ -281,7 +281,7 @@

#define IAP_CODE_LEN 0x34

#define LPC11xx_REG_SECTORS 24
#define LPC11XX_REG_SECTORS 24

typedef enum {
lpc2000_v1,
@@ -590,9 +590,9 @@ static int lpc2000_build_sector_list(struct flash_bank *bank)
unsigned int large_sectors = 0;
unsigned int normal_sectors = bank->size / 4096;

if (normal_sectors > LPC11xx_REG_SECTORS) {
large_sectors = (normal_sectors - LPC11xx_REG_SECTORS) / 8;
normal_sectors = LPC11xx_REG_SECTORS;
if (normal_sectors > LPC11XX_REG_SECTORS) {
large_sectors = (normal_sectors - LPC11XX_REG_SECTORS) / 8;
normal_sectors = LPC11XX_REG_SECTORS;
}

bank->num_sectors = normal_sectors + large_sectors;
@@ -601,7 +601,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank)

for (unsigned int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = offset;
bank->sectors[i].size = (i < LPC11xx_REG_SECTORS ? 4 : 32) * 1024;
bank->sectors[i].size = (i < LPC11XX_REG_SECTORS ? 4 : 32) * 1024;
offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;


+ 4
- 4
src/flash/nor/numicro.c View File

@@ -151,7 +151,7 @@ struct numicro_cpu_type {
{NUMICRO_CONFIG_BASE, 1024} }


static const struct numicro_cpu_type NuMicroParts[] = {
static const struct numicro_cpu_type numicro_parts[] = {
/*PART NO*/ /*PART ID*/ /*Banks*/
/* NUC100 Version B */
{"NUC100LD2BN", 0x10010004, NUMICRO_BANKS_NUC100(64*1024)},
@@ -1648,9 +1648,9 @@ static int numicro_get_cpu_type(struct target *target, const struct numicro_cpu_

LOG_INFO("Device ID: 0x%08" PRIx32 "", part_id);
/* search part numbers */
for (size_t i = 0; i < ARRAY_SIZE(NuMicroParts); i++) {
if (part_id == NuMicroParts[i].partid) {
*cpu = &NuMicroParts[i];
for (size_t i = 0; i < ARRAY_SIZE(numicro_parts); i++) {
if (part_id == numicro_parts[i].partid) {
*cpu = &numicro_parts[i];
LOG_INFO("Device Name: %s", (*cpu)->partname);
return ERROR_OK;
}


+ 25
- 25
src/flash/nor/pic32mx.c View File

@@ -46,11 +46,11 @@
* Note: These macros only work for KSEG0/KSEG1 addresses.
*/

#define Virt2Phys(v) ((v) & 0x1FFFFFFF)
#define virt2phys(v) ((v) & 0x1FFFFFFF)

/* pic32mx configuration register locations */

#define PIC32MX_DEVCFG0_1xx_2xx 0xBFC00BFC
#define PIC32MX_DEVCFG0_1XX_2XX 0xBFC00BFC
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define PIC32MX_DEVCFG1 0xBFC02FF8
#define PIC32MX_DEVCFG2 0xBFC02FF4
@@ -91,8 +91,8 @@
#define NVMKEY1 0xAA996655
#define NVMKEY2 0x556699AA

#define MX_1xx_2xx 1 /* PIC32mx1xx/2xx */
#define MX_17x_27x 2 /* PIC32mx17x/27x */
#define MX_1XX_2XX 1 /* PIC32mx1xx/2xx */
#define MX_17X_27X 2 /* PIC32mx17x/27x */

struct pic32mx_flash_bank {
bool probed;
@@ -279,9 +279,9 @@ static int pic32mx_protect_check(struct flash_bank *bank)
}

switch (pic32mx_info->dev_type) {
case MX_1xx_2xx:
case MX_17x_27x:
config0_address = PIC32MX_DEVCFG0_1xx_2xx;
case MX_1XX_2XX:
case MX_17X_27X:
config0_address = PIC32MX_DEVCFG0_1XX_2XX;
break;
default:
config0_address = PIC32MX_DEVCFG0;
@@ -292,7 +292,7 @@ static int pic32mx_protect_check(struct flash_bank *bank)

if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
num_pages = 0xffff; /* All pages protected */
else if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
else if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
if (devcfg0 & (1 << 24))
num_pages = 0; /* All pages unprotected */
else
@@ -300,10 +300,10 @@ static int pic32mx_protect_check(struct flash_bank *bank)
} else {
/* pgm flash */
switch (pic32mx_info->dev_type) {
case MX_1xx_2xx:
case MX_1XX_2XX:
num_pages = (~devcfg0 >> 10) & 0x7f;
break;
case MX_17x_27x:
case MX_17X_27X:
num_pages = (~devcfg0 >> 10) & 0x1ff;
break;
default:
@@ -332,7 +332,7 @@ static int pic32mx_erase(struct flash_bank *bank, unsigned int first,
}

if ((first == 0) && (last == (bank->num_sectors - 1))
&& (Virt2Phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
&& (virt2phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
/* this will only erase the Program Flash (PFM), not the Boot Flash (BFM)
* we need to use the MTAP to perform a full erase */
LOG_DEBUG("Erasing entire program flash");
@@ -345,7 +345,7 @@ static int pic32mx_erase(struct flash_bank *bank, unsigned int first,
}

for (unsigned int i = first; i <= last; i++) {
target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
target_write_u32(target, PIC32MX_NVMADDR, virt2phys(bank->base + bank->sectors[i].offset));

status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);

@@ -465,8 +465,8 @@ static int pic32mx_write_block(struct flash_bank *bank, const uint8_t *buffer,

/* Change values for counters and row size, depending on variant */
switch (pic32mx_info->dev_type) {
case MX_1xx_2xx:
case MX_17x_27x:
case MX_1XX_2XX:
case MX_17X_27X:
/* 128 byte row */
pic32mx_flash_write_code[8] = 0x2CD30020;
pic32mx_flash_write_code[14] = 0x24840080;
@@ -548,8 +548,8 @@ static int pic32mx_write_block(struct flash_bank *bank, const uint8_t *buffer,
break;
}

buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address));
buf_set_u32(reg_params[0].value, 0, 32, virt2phys(source->address));
buf_set_u32(reg_params[1].value, 0, 32, virt2phys(address));
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);

retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
@@ -599,7 +599,7 @@ static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_
{
struct target *target = bank->target;

target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(address));
target_write_u32(target, PIC32MX_NVMADDR, virt2phys(address));
target_write_u32(target, PIC32MX_NVMDATA, word);

return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
@@ -717,14 +717,14 @@ static int pic32mx_probe(struct flash_bank *bank)
for (i = 0; pic32mx_devs[i].name != NULL; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
if ((pic32mx_devs[i].name[0] == '1') || (pic32mx_devs[i].name[0] == '2'))
pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17x_27x : MX_1xx_2xx;
pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17X_27X : MX_1XX_2XX;
break;
}
}

switch (pic32mx_info->dev_type) {
case MX_1xx_2xx:
case MX_17x_27x:
case MX_1XX_2XX:
case MX_17X_27X:
page_size = 1024;
break;
default:
@@ -732,7 +732,7 @@ static int pic32mx_probe(struct flash_bank *bank)
break;
}

if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
/* 0x1FC00000: Boot flash size */
#if 0
/* for some reason this register returns 8k for the boot bank size
@@ -745,8 +745,8 @@ static int pic32mx_probe(struct flash_bank *bank)
#else
/* fixed 12k boot bank - see comments above */
switch (pic32mx_info->dev_type) {
case MX_1xx_2xx:
case MX_17x_27x:
case MX_1XX_2XX:
case MX_17X_27X:
num_pages = (3 * 1024);
break;
default:
@@ -758,8 +758,8 @@ static int pic32mx_probe(struct flash_bank *bank)
/* read the flash size from the device */
if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
switch (pic32mx_info->dev_type) {
case MX_1xx_2xx:
case MX_17x_27x:
case MX_1XX_2XX:
case MX_17X_27X:
LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
num_pages = (32 * 1024);
break;


+ 11
- 11
src/flash/nor/psoc5lp.c View File

@@ -86,15 +86,15 @@

#define PM_ACT_CFG0_EN_CLK_SPC (1 << 3)

#define PHUB_CHx_BASIC_CFG_EN (1 << 0)
#define PHUB_CHx_BASIC_CFG_WORK_SEP (1 << 5)
#define PHUB_CHX_BASIC_CFG_EN (1 << 0)
#define PHUB_CHX_BASIC_CFG_WORK_SEP (1 << 5)

#define PHUB_CHx_ACTION_CPU_REQ (1 << 0)
#define PHUB_CHX_ACTION_CPU_REQ (1 << 0)

#define PHUB_CFGMEMx_CFG0 (1 << 7)
#define PHUB_CFGMEMX_CFG0 (1 << 7)

#define PHUB_TDMEMx_ORIG_TD0_NEXT_TD_PTR_LAST (0xff << 16)
#define PHUB_TDMEMx_ORIG_TD0_INC_SRC_ADDR (1 << 24)
#define PHUB_TDMEMX_ORIG_TD0_NEXT_TD_PTR_LAST (0xff << 16)
#define PHUB_TDMEMX_ORIG_TD0_INC_SRC_ADDR (1 << 24)

#define NVL_3_ECCEN (1 << 3)

@@ -1289,13 +1289,13 @@ static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer,

retval = target_write_u32(target,
even_row ? PHUB_CH0_BASIC_CFG : PHUB_CH1_BASIC_CFG,
PHUB_CHx_BASIC_CFG_WORK_SEP | PHUB_CHx_BASIC_CFG_EN);
PHUB_CHX_BASIC_CFG_WORK_SEP | PHUB_CHX_BASIC_CFG_EN);
if (retval != ERROR_OK)
goto err_dma;

retval = target_write_u32(target,
even_row ? PHUB_CFGMEM0_CFG0 : PHUB_CFGMEM1_CFG0,
PHUB_CFGMEMx_CFG0);
PHUB_CFGMEMX_CFG0);
if (retval != ERROR_OK)
goto err_dma;

@@ -1307,8 +1307,8 @@ static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer,

retval = target_write_u32(target,
even_row ? PHUB_TDMEM0_ORIG_TD0 : PHUB_TDMEM1_ORIG_TD0,
PHUB_TDMEMx_ORIG_TD0_INC_SRC_ADDR |
PHUB_TDMEMx_ORIG_TD0_NEXT_TD_PTR_LAST |
PHUB_TDMEMX_ORIG_TD0_INC_SRC_ADDR |
PHUB_TDMEMX_ORIG_TD0_NEXT_TD_PTR_LAST |
((SPC_OPCODE_LEN + 1 + row_size + 3 + SPC_OPCODE_LEN + 5) & 0xfff));
if (retval != ERROR_OK)
goto err_dma;
@@ -1325,7 +1325,7 @@ static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer,

retval = target_write_u32(target,
even_row ? PHUB_CH0_ACTION : PHUB_CH1_ACTION,
PHUB_CHx_ACTION_CPU_REQ);
PHUB_CHX_ACTION_CPU_REQ);
if (retval != ERROR_OK)
goto err_dma_action;
}


+ 7
- 7
src/flash/nor/stellaris.c View File

@@ -126,7 +126,7 @@ static const struct {
uint8_t class;
uint8_t partno;
const char *partname;
} StellarisParts[] = {
} stellaris_parts[] = {
{0x00, 0x01, "LM3S101"},
{0x00, 0x02, "LM3S102"},
{0x01, 0xBF, "LM3S1110"},
@@ -436,7 +436,7 @@ static const struct {
{0xFF, 0x00, "Unknown Part"}
};

static const char * const StellarisClassname[] = {
static const char * const stellaris_classname[] = {
"Sandstorm",
"Fury",
"Unknown",
@@ -493,7 +493,7 @@ static int get_stellaris_info(struct flash_bank *bank, struct command_invocation
"\nTI/LMI Stellaris information: Chip is "
"class %i (%s) %s rev %c%i\n",
stellaris_info->target_class,
StellarisClassname[stellaris_info->target_class],
stellaris_classname[stellaris_info->target_class],
stellaris_info->target_name,
(int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
(int)((stellaris_info->did0) & 0xFF));
@@ -743,13 +743,13 @@ static int stellaris_read_part_info(struct flash_bank *bank)
LOG_WARNING("Unknown did0 class");
}

for (i = 0; StellarisParts[i].partno; i++) {
if ((StellarisParts[i].partno == ((did1 >> 16) & 0xFF)) &&
(StellarisParts[i].class == stellaris_info->target_class))
for (i = 0; stellaris_parts[i].partno; i++) {
if ((stellaris_parts[i].partno == ((did1 >> 16) & 0xFF)) &&
(stellaris_parts[i].class == stellaris_info->target_class))
break;
}

stellaris_info->target_name = StellarisParts[i].partname;
stellaris_info->target_name = stellaris_parts[i].partname;

stellaris_info->did0 = did0;
stellaris_info->did1 = did1;


+ 9
- 9
src/flash/nor/str7x.c View File

@@ -720,8 +720,8 @@ COMMAND_HANDLER(str7x_handle_disable_jtag_command)
struct str7x_flash_bank *str7x_info = NULL;

uint32_t flash_cmd;
uint16_t ProtectionLevel = 0;
uint16_t ProtectionRegs;
uint16_t protection_level = 0;
uint16_t protection_regs;

if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -745,17 +745,17 @@ COMMAND_HANDLER(str7x_handle_disable_jtag_command)
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);

if (!(reg & str7x_info->disable_bit))
ProtectionLevel = 1;
protection_level = 1;

target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
ProtectionRegs = ~(reg >> 16);
protection_regs = ~(reg >> 16);

while (((ProtectionRegs) != 0) && (ProtectionLevel < 16)) {
ProtectionRegs >>= 1;
ProtectionLevel++;
while (((protection_regs) != 0) && (protection_level < 16)) {
protection_regs >>= 1;
protection_level++;
}

if (ProtectionLevel == 0) {
if (protection_level == 0) {
flash_cmd = FLASH_SPR;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
@@ -767,7 +767,7 @@ COMMAND_HANDLER(str7x_handle_disable_jtag_command)
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
~(1 << (15 + ProtectionLevel)));
~(1 << (15 + protection_level)));
flash_cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
}


+ 18
- 18
src/flash/nor/tms470.c View File

@@ -285,8 +285,8 @@ static int tms470_read_part_info(struct flash_bank *bank)

/* ---------------------------------------------------------------------- */

static uint32_t keysSet;
static uint32_t flashKeys[4];
static uint32_t keys_set;
static uint32_t flash_keys[4];

COMMAND_HANDLER(tms470_handle_flash_keyset_command)
{
@@ -298,7 +298,7 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command)
for (i = 0; i < 4; i++) {
int start = (0 == strncmp(CMD_ARGV[i], "0x", 2)) ? 2 : 0;

if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flashKeys[i])) {
if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i])) {
command_print(CMD, "could not process flash key %s",
CMD_ARGV[i]);
LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
@@ -306,19 +306,19 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command)
}
}

keysSet = 1;
keys_set = 1;
} else if (CMD_ARGC != 0) {
command_print(CMD, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
return ERROR_COMMAND_SYNTAX_ERROR;
}

if (keysSet) {
if (keys_set) {
command_print(CMD,
"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
flashKeys[0],
flashKeys[1],
flashKeys[2],
flashKeys[3]);
flash_keys[0],
flash_keys[1],
flash_keys[2],
flash_keys[3]);
} else
command_print(CMD, "flash keys not set");

@@ -471,9 +471,9 @@ static int tms470_unlock_flash(struct flash_bank *bank)
const uint32_t *p_key_sets[5];
unsigned i, key_set_count;

if (keysSet) {
if (keys_set) {
key_set_count = 5;
p_key_sets[0] = flashKeys;
p_key_sets[0] = flash_keys;
p_key_sets[1] = FLASH_KEYS_ALL_ONES;
p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
p_key_sets[3] = FLASH_KEYS_MIX1;
@@ -685,7 +685,7 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
{
uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
struct target *target = bank->target;
uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
uint32_t flash_addr = bank->base + bank->sectors[sector].offset;
int result = ERROR_OK;

/*
@@ -722,12 +722,12 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
/*
* clear status register, sent erase command, kickoff erase
*/
target_write_u16(target, flashAddr, 0x0040);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
target_write_u16(target, flashAddr, 0x0020);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flashAddr);
target_write_u16(target, flashAddr, 0xffff);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flashAddr);
target_write_u16(target, flash_addr, 0x0040);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flash_addr);
target_write_u16(target, flash_addr, 0x0020);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flash_addr);
target_write_u16(target, flash_addr, 0xffff);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flash_addr);

/*
* Monitor FMMSTAT, busy until clear, then check and other flags for


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