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David Brownell <david-b@pacbell.net>

Update the board config for the DaVinci DM355 EVM so the reset-init
event handler does the rest of the work it should do:

 - minor PLL setup bugfixes
 - initialize the DDR2 controller
 - probe both NAND banks
 - initialize UART0
 - enable the icache


git-svn-id: svn://svn.berlios.de/openocd/trunk@2699 b42882b7-edfa-0310-969c-e2dbd0fdcd60
tags/v0.3.0-rc0
oharboe 13 years ago
parent
commit
40f361dd94
3 changed files with 96 additions and 4 deletions
  1. +84
    -3
      tcl/board/dm355evm.cfg
  2. +9
    -1
      tcl/target/davinci.cfg
  3. +3
    -0
      tcl/target/ti_dm355.cfg

+ 84
- 3
tcl/board/dm355evm.cfg View File

@@ -35,7 +35,7 @@ proc dm355evm_init {} {
set addr [dict get $dm355 pllc1]
set pll_divs [dict create]
dict set pll_divs div3 16
dict set pll_divs div4 8
dict set pll_divs div4 4
pll_v02_setup $addr 144 $pll_divs

# ARM is now running at 216 MHz, so JTAG can go faster
@@ -48,6 +48,7 @@ proc dm355evm_init {} {

set addr [dict get $dm355 pllc2]
set pll_divs [dict create]
dict set pll_divs div1 1
dict set pll_divs prediv 8
pll_v02_setup $addr 114 $pll_divs

@@ -77,7 +78,54 @@ proc dm355evm_init {} {
########################
# DDR2 EMIF

# FIXME setup
# VTPIOCR impedance calibration
set addr [dict get $dm355 sysbase]
set addr [expr $addr + 0x70]

# clear CLR, LOCK, PWRDN; wait a clock; set CLR
mmw $addr 0 0x20c0
mmw $addr 0x2000 0

# wait for READY
while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }

# set IO_READY; then LOCK and PWRSAVE; then PWRDN
mmw $addr 0x4000 0
mmw $addr 0x0180 0
mmw $addr 0x0040 0

# NOTE: this DDR2 initialization sequence borrows from
# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.

# reset (then re-enable) DDR controller
psc_reset 13
psc_go
psc_enable 13
psc_go

# now set it up for Micron MT47H64M16HR-37E @ 171 MHz

set addr [dict get $dm355 ddr_emif]

# DDRPHYCR1
mww [expr $addr + 0xe4] 0x50006404

# PBBPR -- burst priority
mww [expr $addr + 0x20] 0xfe

# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
mmw [expr $addr + 0x08] 0x00800000 0
mmw [expr $addr + 0x08] 0x0013c632 0x03870fff

# SDTIMR, SDTIMR2
mww [expr $addr + 0x10] 0x2a923249
mww [expr $addr + 0x14] 0x4c17c763

# SDCR -- relock SDTIM*
mmw [expr $addr + 0x08] 0 0x00008000

# SDRCR -- refresh rate (171 MHz * 7.8usec)
mww [expr $addr + 0x0c] 1336

########################
# ASYNC EMIF
@@ -98,10 +146,43 @@ proc dm355evm_init {} {
# NANDFCR -- only CS0 has NAND
mww [expr $addr + 0x60] 0x01

# default: both chipselects to the NAND socket are used
nand probe 0
nand probe 1

########################
# UART0

# FIXME setup
set addr [dict get $dm355 uart0]

# PWREMU_MGNT -- rx + tx in reset
mww [expr $addr + 0x30] 0

# DLL, DLH -- 115200 baud
mwb [expr $addr + 0x20] 0x0d
mwb [expr $addr + 0x24] 0x00

# FCR - clear and disable FIFOs
mwb [expr $addr + 0x08] 0x07
mwb [expr $addr + 0x08] 0x00

# IER - disable IRQs
mwb [expr $addr + 0x04] 0x00

# LCR - 8-N-1
mwb [expr $addr + 0x0c] 0x03

# MCR - no flow control or loopback
mwb [expr $addr + 0x10] 0x00

# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
mww [expr $addr + 0x30] 0xe001


########################

# turn on icache - set I bit in cp15 register c1
arm926ejs cp15 0 0 1 0 0x00051078
}

# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.


+ 9
- 1
tcl/target/davinci.cfg View File

@@ -125,6 +125,7 @@ proc pll_v02_setup {pll_addr mult config} {
set pllstat [expr $pll_addr + 0x013c]
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
}
mww [expr $pll_addr + 0x0138] 0x00

# 11 - wait at least 5 usec for reset to finish
# (assume covered by overheads including JTAG messaging)
@@ -152,7 +153,14 @@ proc psc_enable {module} {
mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
}

# execute non-DSP PSC transition(s) set up by psc_enable
# prepare a non-DSP module to be reset; finish with psc_go
proc psc_reset {module} {
set psc_addr 0x01c41000
# write MDCTL
mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
}

# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
proc psc_go {} {
set psc_addr 0x01c41000
set ptstat_addr [expr $psc_addr + 0x0128]


+ 3
- 0
tcl/target/ti_dm355.cfg View File

@@ -65,6 +65,9 @@ dict set dm355 a_emif_cs0 0x02000000
dict set dm355 a_emif_cs1 0x04000000
dict set dm355 ddr_emif 0x20000000
dict set dm355 ddr 0x80000000
dict set dm355 uart0 0x01c20000
dict set dm355 uart1 0x01c20400
dict set dm355 uart2 0x01e06000

source [find target/davinci.cfg]



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