git-svn-id: svn://svn.berlios.de/openocd/trunk@2756 b42882b7-edfa-0310-969c-e2dbd0fdcd60tags/v0.3.0-rc0
@@ -0,0 +1,118 @@ | |||
###################################### | |||
# Target: Toshiba TOPAS910 -- TMPA910 Starterkit | |||
# | |||
###################################### | |||
# We add to the minimal configuration. | |||
source [find target/tmpa910.cfg] | |||
###################### | |||
# Target configuration | |||
###################### | |||
#$_TARGETNAME configure -event gdb-attach { reset init } | |||
$_TARGETNAME configure -event reset-init { topas910_init } | |||
proc topas910_init { } { | |||
# Init PLL | |||
# my settings | |||
mww 0xf005000c 0x00000007 | |||
mww 0xf0050010 0x00000065 | |||
mww 0xf005000c 0x000000a7 | |||
sleep 10 | |||
mdw 0xf0050008 | |||
mww 0xf0050008 0x00000002 | |||
mww 0xf0050004 0x00000000 | |||
# NEW: set CLKCR5 | |||
mww 0xf0050054 0x00000040 | |||
# | |||
sleep 10 | |||
# Init SDRAM | |||
# _PMCDRV = 0x00000071; | |||
# // | |||
# // Initialize SDRAM timing paramater | |||
# // | |||
# _DMC_CAS_LATENCY = 0x00000006; | |||
# _DMC_T_DQSS = 0x00000000; | |||
# _DMC_T_MRD = 0x00000002; | |||
# _DMC_T_RAS = 0x00000007; | |||
# | |||
# _DMC_T_RC = 0x0000000A; | |||
# _DMC_T_RCD = 0x00000013; | |||
# | |||
# _DMC_T_RFC = 0x0000010A; | |||
# | |||
# _DMC_T_RP = 0x00000013; | |||
# _DMC_T_RRD = 0x00000002; | |||
# _DMC_T_WR = 0x00000002; | |||
# _DMC_T_WTR = 0x00000001; | |||
# _DMC_T_XP = 0x0000000A; | |||
# _DMC_T_XSR = 0x0000000B; | |||
# _DMC_T_ESR = 0x00000014; | |||
# | |||
# // | |||
# // Configure SDRAM type parameter | |||
# _DMC_MEMORY_CFG = 0x00008011; | |||
# _DMC_USER_CONFIG = 0x00000011; | |||
# // 32 bit memory interface | |||
# | |||
# | |||
# _DMC_REFRESH_PRD = 0x00000A60; | |||
# _DMC_CHIP_0_CFG = 0x000140FC; | |||
# | |||
# _DMC_DIRECT_CMD = 0x000C0000; | |||
# _DMC_DIRECT_CMD = 0x00000000; | |||
# | |||
# _DMC_DIRECT_CMD = 0x00040000; | |||
# _DMC_DIRECT_CMD = 0x00040000; | |||
# _DMC_DIRECT_CMD = 0x00080031; | |||
# // | |||
# // Finally start SDRAM | |||
# // | |||
# _DMC_MEMC_CMD = MEMC_CMD_GO; | |||
# */ | |||
mww 0xf0020260 0x00000071 | |||
mww 0xf4300014 0x00000006 | |||
mww 0xf4300018 0x00000000 | |||
mww 0xf430001C 0x00000002 | |||
mww 0xf4300020 0x00000007 | |||
mww 0xf4300024 0x0000000A | |||
mww 0xf4300028 0x00000013 | |||
mww 0xf430002C 0x0000010A | |||
mww 0xf4300030 0x00000013 | |||
mww 0xf4300034 0x00000002 | |||
mww 0xf4300038 0x00000002 | |||
mww 0xf430003C 0x00000001 | |||
mww 0xf4300040 0x0000000A | |||
mww 0xf4300044 0x0000000B | |||
mww 0xf4300048 0x00000014 | |||
mww 0xf430000C 0x00008011 | |||
mww 0xf4300304 0x00000011 | |||
mww 0xf4300010 0x00000A60 | |||
mww 0xf4300200 0x000140FC | |||
mww 0xf4300008 0x000C0000 | |||
mww 0xf4300008 0x00000000 | |||
mww 0xf4300008 0x00040000 | |||
mww 0xf4300008 0x00040000 | |||
mww 0xf4300008 0x00080031 | |||
mww 0xf4300004 0x00000000 | |||
sleep 10 | |||
# jtag_speed 10000 | |||
# remap off in case of IROM boot | |||
mww 0xf0000004 0x00000001 | |||
} | |||
# comment the following out if usinf J-Link, it soes not support DCC | |||
arm7_9 dcc_downloads enable # Enable faster DCC downloads | |||
##################### | |||
# Flash configuration | |||
##################### | |||
#flash bank cfi <base> <size> <chip width> <bus width> <target#> | |||
flash bank cfi 0x20000000 0x2000000 2 2 0 |
@@ -0,0 +1,125 @@ | |||
# Thanks to Pieter Conradie for this script! | |||
# Target: Toshiba TOPAS900 -- TMPA900 Starterkit | |||
###################################### | |||
# We add to the minimal configuration. | |||
source [find target/tmpa900.cfg] | |||
###################### | |||
# Target configuration | |||
###################### | |||
#$_TARGETNAME configure -event gdb-attach { reset init } | |||
$_TARGETNAME configure -event reset-init { topasa900_init } | |||
proc topasa900_init { } { | |||
# Init PLL | |||
# my settings | |||
mww 0xf005000c 0x00000007 | |||
mww 0xf0050010 0x00000065 | |||
mww 0xf005000c 0x000000a7 | |||
sleep 10 | |||
mdw 0xf0050008 | |||
mww 0xf0050008 0x00000002 | |||
mww 0xf0050004 0x00000000 | |||
# NEW: set CLKCR5 | |||
mww 0xf0050054 0x00000040 | |||
# | |||
# bplan settings | |||
# mww 0xf0050004 0x00000000 | |||
# mww 0xf005000c 0x000000a7 | |||
# sleep 10 | |||
# mdw 0xf0050008 | |||
# mww 0xf0050008 0x00000002 | |||
# mww 0xf0050010 0x00000065 | |||
# mww 0xf0050054 0x00000040 | |||
sleep 10 | |||
# Init SDRAM | |||
# _PMCDRV = 0x00000071; | |||
# // | |||
# // Initialize SDRAM timing paramater | |||
# // | |||
# _DMC_CAS_LATENCY = 0x00000006; | |||
# _DMC_T_DQSS = 0x00000000; | |||
# _DMC_T_MRD = 0x00000002; | |||
# _DMC_T_RAS = 0x00000007; | |||
# | |||
# _DMC_T_RC = 0x0000000A; | |||
# _DMC_T_RCD = 0x00000013; | |||
# | |||
# _DMC_T_RFC = 0x0000010A; | |||
# | |||
# _DMC_T_RP = 0x00000013; | |||
# _DMC_T_RRD = 0x00000002; | |||
# _DMC_T_WR = 0x00000002; | |||
# _DMC_T_WTR = 0x00000001; | |||
# _DMC_T_XP = 0x0000000A; | |||
# _DMC_T_XSR = 0x0000000B; | |||
# _DMC_T_ESR = 0x00000014; | |||
# | |||
# // | |||
# // Configure SDRAM type parameter | |||
# _DMC_MEMORY_CFG = 0x00008011; | |||
# _DMC_USER_CONFIG = 0x00000011; // 32 bit memory interface | |||
# | |||
# | |||
# _DMC_REFRESH_PRD = 0x00000A60; | |||
# _DMC_CHIP_0_CFG = 0x000140FC; | |||
# | |||
# _DMC_DIRECT_CMD = 0x000C0000; | |||
# _DMC_DIRECT_CMD = 0x00000000; | |||
# | |||
# _DMC_DIRECT_CMD = 0x00040000; | |||
# _DMC_DIRECT_CMD = 0x00040000; | |||
# _DMC_DIRECT_CMD = 0x00080031; | |||
# // | |||
# // Finally start SDRAM | |||
# // | |||
# _DMC_MEMC_CMD = MEMC_CMD_GO; | |||
# */ | |||
mww 0xf0020260 0x00000071 | |||
mww 0xf4300014 0x00000006 | |||
mww 0xf4300018 0x00000000 | |||
mww 0xf430001C 0x00000002 | |||
mww 0xf4300020 0x00000007 | |||
mww 0xf4300024 0x0000000A | |||
mww 0xf4300028 0x00000013 | |||
mww 0xf430002C 0x0000010A | |||
mww 0xf4300030 0x00000013 | |||
mww 0xf4300034 0x00000002 | |||
mww 0xf4300038 0x00000002 | |||
mww 0xf430003C 0x00000001 | |||
mww 0xf4300040 0x0000000A | |||
mww 0xf4300044 0x0000000B | |||
mww 0xf4300048 0x00000014 | |||
mww 0xf430000C 0x00008011 | |||
mww 0xf4300304 0x00000011 | |||
mww 0xf4300010 0x00000A60 | |||
mww 0xf4300200 0x000140FC | |||
mww 0xf4300008 0x000C0000 | |||
mww 0xf4300008 0x00000000 | |||
mww 0xf4300008 0x00040000 | |||
mww 0xf4300008 0x00040000 | |||
mww 0xf4300008 0x00080031 | |||
mww 0xf4300004 0x00000000 | |||
sleep 10 | |||
# jtag_speed 10000 | |||
# remap off in case of IROM boot | |||
mww 0xf0000004 0x00000001 | |||
} | |||
# comment the following out if usinf J-Link, it soes not support DCC | |||
arm7_9 dcc_downloads enable # Enable faster DCC downloads | |||
##################### | |||
# Flash configuration | |||
##################### | |||
#flash bank cfi <base> <size> <chip width> <bus width> <target#> | |||
flash bank cfi 0x20000000 0x1000000 2 2 0 | |||
@@ -0,0 +1,56 @@ | |||
###################################### | |||
# Target: Toshiba TMPA910 | |||
###################################### | |||
if { [info exists CHIPNAME] } { | |||
set _CHIPNAME $CHIPNAME | |||
} else { | |||
set _CHIPNAME tmpa910 | |||
} | |||
if { [info exists ENDIAN] } { | |||
set _ENDIAN $ENDIAN | |||
} else { | |||
set _ENDIAN little | |||
} | |||
if { [info exists CPUTAPID ] } { | |||
set _CPUTAPID $CPUTAPID | |||
} else { | |||
# force an error till we get a good number | |||
set _CPUTAPID 0x07926031 | |||
} | |||
#TMPA910 has following IDs: | |||
# CP15.0 register 0x41069265 | |||
# CP15.1 register 0x1d152152 | |||
# ARM core 0x07926031 | |||
# | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
#use combined on interfaces or targets that can't set TRST/SRST separately | |||
reset_config trst_and_srst | |||
jtag_nsrst_delay 20 | |||
jtag_ntrst_delay 20 | |||
###################### | |||
# Target configuration | |||
###################### | |||
set _TARGETNAME [format "%s.cpu" $_CHIPNAME] | |||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs | |||
# built-in RAM0 | |||
#working_area 0 0xf8004000 0x4000 nobackup | |||
# built-in RAM1 | |||
#working_area 1 0xf8008000 0x4000 nobackup | |||
# built-in RAM2 | |||
#working_area 2 0xf800c000 0x4000 nobackup | |||
# built-in RAM 0-2 48k total | |||
#working_area 0 0xf8004000 0xc000 nobackup | |||
# Internal sram1 memory | |||
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xf8004000 -work-area-size 0x8000 \ | |||
-work-area-backup 0 |
@@ -0,0 +1,56 @@ | |||
###################################### | |||
# Target: Toshiba TMPA910 | |||
###################################### | |||
if { [info exists CHIPNAME] } { | |||
set _CHIPNAME $CHIPNAME | |||
} else { | |||
set _CHIPNAME tmpa910 | |||
} | |||
if { [info exists ENDIAN] } { | |||
set _ENDIAN $ENDIAN | |||
} else { | |||
set _ENDIAN little | |||
} | |||
if { [info exists CPUTAPID ] } { | |||
set _CPUTAPID $CPUTAPID | |||
} else { | |||
# force an error till we get a good number | |||
set _CPUTAPID 0x07926031 | |||
} | |||
#TMPA910 has following IDs: | |||
# CP15.0 register 0x41069265 | |||
# CP15.1 register 0x1d152152 | |||
# ARM core 0x07926031 | |||
# | |||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |||
#use combined on interfaces or targets that can't set TRST/SRST separately | |||
reset_config trst_and_srst | |||
jtag_nsrst_delay 20 | |||
jtag_ntrst_delay 20 | |||
###################### | |||
# Target configuration | |||
###################### | |||
set _TARGETNAME [format "%s.cpu" $_CHIPNAME] | |||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs | |||
# built-in RAM0 | |||
#working_area 0 0xf8004000 0x4000 nobackup | |||
# built-in RAM1 | |||
#working_area 1 0xf8008000 0x4000 nobackup | |||
# built-in RAM2 | |||
#working_area 2 0xf800c000 0x4000 nobackup | |||
# built-in RAM 0-2 48k total | |||
#working_area 0 0xf8004000 0xc000 nobackup | |||
# Internal sram1 memory | |||
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xf8004000 -work-area-size 0xc000 \ | |||
-work-area-backup 0 |