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iMX target config script's ported from Freescale BSP.

tags/v0.3.0-rc0
Øyvind Harboe 12 years ago
parent
commit
44e9200d0a
3 changed files with 57 additions and 65 deletions
  1. +25
    -39
      tcl/board/imx31pdk.cfg
  2. +2
    -26
      tcl/board/imx35pdk.cfg
  3. +30
    -0
      tcl/target/imx.cfg

+ 25
- 39
tcl/board/imx31pdk.cfg View File

@@ -1,59 +1,47 @@
# The IMX31PDK eval board has a single IMX31 chip
source [find target/imx31.cfg]
source [find target/imx.cfg]
$_TARGETNAME configure -event reset-init { imx31pdk_init }

proc imx31pdk_init { } {

imx3x_reset

# This setup puts RAM at 0x80000000

# ========================================
# Init CCM
# ========================================
mww 0x53FC0000 0x040
mww 0x53F80000 0x074B0B7D

sleep 100

# ========================================
# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
# ========================================
mww 0x53F80004 0xFF871D50
mww 0x53F80010 0x00271C1B

# ========================================
# Configure CPLD on CS5
# ========================================
mww 0xb8002050 0x0000DCF6
mww 0xb8002054 0x444A4541
mww 0xb8002058 0x44443302

# ========================================
#mww 0x53F80004 0xFF871D50
#mww 0x53F80010 0x00271C1B
# Start 16 bit NorFlash Initialization on CS0
mww 0xb8002000 0x0000CC03
mww 0xb8002004 0xa0330D01
mww 0xb8002008 0x00220800
# Configure CPLD on CS4
mww 0xb8002040 0x0000DCF6
mww 0xb8002044 0x444A4541
mww 0xb8002048 0x44443302
# SDCLK
# ========================================
mww 0x43FAC26C 0

# ========================================
# CAS
# ========================================
mww 0x43FAC270 0

# ========================================
# RAS
# ========================================
mww 0x43FAC274 0

# ========================================
# CS2 (CSD0)
# ========================================
mww 0x43FAC27C 0x1000

# ========================================
# DQM3
# ========================================
mww 0x43FAC284 0

# ========================================
# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
# ========================================
mww 0x43FAC288 0
mww 0x43FAC28C 0
mww 0x43FAC290 0
@@ -76,10 +64,8 @@ proc imx31pdk_init { } {
mww 0x43FAC2D4 0
mww 0x43FAC2D8 0
mww 0x43FAC2DC 0

# ========================================
# Initialization script for 32 bit DDR on MX31 PDK
# ========================================
# Initialization script for 32 bit DDR on MX31 ADS
mww 0xB8001010 0x00000004
mww 0xB8001004 0x006ac73a
mww 0xB8001000 0x92100000


+ 2
- 26
tcl/board/imx35pdk.cfg View File

@@ -1,35 +1,11 @@
# The IMX35PDK eval board has a single IMX35 chip
source [find target/imx35.cfg]
source [find target/imx.cfg]
$_TARGETNAME configure -event reset-init { imx35pdk_init }


global TARGETNAME
set TARGETNAME $_TARGETNAME

# rewrite commands of the form below to arm11 mcr...
# Data.Set c15:0x042f %long 0x40000015
proc setc15 {regs value} {
global TARGETNAME

echo [format "set p15 0x%04x, 0x%08x" $regs $value]

arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
}

proc imx35pdk_init { } {
# this reset script comes from the Freescale PDK
#
# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
echo "Target Setup: initialize DRAM controller and peripherals"
# Data.Set c15:0x01 %long 0x00050078
setc15 0x01 0x00050078
echo "configuring CP15 for enabling the peripheral bus"
# Data.Set c15:0x042f %long 0x40000015
setc15 0x042f 0x40000015
imx3x_reset
mww 0x43f00040 0x00000000
mww 0x43f00044 0x00000000


+ 30
- 0
tcl/target/imx.cfg View File

@@ -0,0 +1,30 @@
# utility fn's for Freescale i.MX series

global TARGETNAME
set TARGETNAME $_TARGETNAME

# rewrite commands of the form below to arm11 mcr...
# Data.Set c15:0x042f %long 0x40000015
proc setc15 {regs value} {
global TARGETNAME

echo [format "set p15 0x%04x, 0x%08x" $regs $value]

arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
}


proc imx3x_reset {} {
# this reset script comes from the Freescale PDK
#
# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
echo "Target Setup: initialize DRAM controller and peripherals"
# Data.Set c15:0x01 %long 0x00050078
setc15 0x01 0x00050078
echo "configuring CP15 for enabling the peripheral bus"
# Data.Set c15:0x042f %long 0x40000015
setc15 0x042f 0x40000015
}

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