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@@ -1779,28 +1779,6 @@ static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, |
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return cortex_a8_write_memory(target, address, 4, count, buffer); |
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} |
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static int cortex_a8_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl) |
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{ |
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#if 0 |
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u16 dcrdr; |
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mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); |
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*ctrl = (uint8_t)dcrdr; |
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*value = (uint8_t)(dcrdr >> 8); |
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LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl); |
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/* write ack back to software dcc register |
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* signify we have read data */ |
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if (dcrdr & (1 << 0)) |
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{ |
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dcrdr = 0; |
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mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); |
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} |
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#endif |
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return ERROR_OK; |
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} |
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static int cortex_a8_handle_target_request(void *priv) |
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{ |
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@@ -1816,33 +1794,22 @@ static int cortex_a8_handle_target_request(void *priv) |
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if (target->state == TARGET_RUNNING) |
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{ |
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uint8_t data = 0; |
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uint8_t ctrl = 0; |
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retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); |
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if (retval != ERROR_OK) |
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return retval; |
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uint32_t request; |
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uint32_t dscr; |
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, |
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armv7a->debug_base + CPUDBG_DSCR, &dscr); |
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/* check if we have data */ |
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if (ctrl & (1 << 0)) |
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while ((dscr & DSCR_DTR_TX_FULL) && (retval==ERROR_OK)) |
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{ |
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uint32_t request; |
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/* we assume target is quick enough */ |
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request = data; |
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retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); |
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if (retval != ERROR_OK) |
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return retval; |
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request |= (data << 8); |
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retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); |
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if (retval != ERROR_OK) |
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return retval; |
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request |= (data << 16); |
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retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); |
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if (retval != ERROR_OK) |
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return retval; |
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request |= (data << 24); |
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target_request(target, request); |
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, |
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armv7a->debug_base+ CPUDBG_DTRTX, &request); |
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if (retval == ERROR_OK) |
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{ |
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target_request(target, request); |
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, |
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armv7a->debug_base+ CPUDBG_DSCR, &dscr); |
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} |
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} |
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} |
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