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@@ -13,25 +13,29 @@ Target Layer: |
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General |
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- new "reset-assert" event, for systems without SRST |
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ARM |
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- supports "reset-assert" event (except on Cortex-M3) |
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- renamed "armv4_5" command prefix as "arm" |
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- recognize TrustZone "Secure Monitor" mode |
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- "arm regs" command output changed |
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- register names use "sp" not "r13" |
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- add top-level "mcr" and "mrc" commands, replacing |
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various core-specific operations |
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- basic semihosting support |
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- basic semihosting support (ARM7/ARM9 only, for now) |
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ARM11 |
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- Preliminary ETM and ETB hookup |
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- accelerated "flash erase_check" |
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- accelerated GDB memory checksum |
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- support "arm regs" command |
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- can access all core modes and registers |
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- watchpoint support |
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- Should act much more like other ARM cores: |
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* Preliminary ETM and ETB hookup |
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* accelerated "flash erase_check" |
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* accelerated GDB memory checksum |
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* support "arm regs" command |
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* can access all core modes and registers |
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* watchpoint support |
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- Shares some core debug code with Cortex-A8 |
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Cortex-A8 |
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- support "arm regs" command |
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- can access all core modes and registers |
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- supports "reset-assert" event (used on OMAP3530) |
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- watchpoint support |
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- Should act much more like other ARM cores: |
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* support "arm regs" command |
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* can access all core modes and registers |
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* watchpoint support |
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- Shares some core debug code with ARM11 |
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Cortex-M3 |
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- Exposed DWT registers like cycle counter |
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- vector_catch settings not clobbered by resets |
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