Transform 'u8' to 'uint8_t' in src/target

- Replace '\([^_]\)u8' with '\1uint8_t'.
- Replace '^u8' with 'uint8_t'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2274 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/algorithm.h

@@ -33,7 +33,7 @@ typedef struct mem_param_s
 {
 	u32 address;
 	u32 size;
-	u8 *value;
+	uint8_t *value;
 	enum param_direction direction;
 } mem_param_t; 
 
@@ -41,7 +41,7 @@ typedef struct reg_param_s
 {
 	char *reg_name;
 	u32 size;
-	u8 *value;
+	uint8_t *value;
 	enum param_direction direction;
 } reg_param_t;
 

src/target/arm11.c

@@ -288,14 +288,14 @@ enum arm11_regcache_ids
 
 #define ARM11_GDB_REGISTER_COUNT	26
 
-u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
 reg_t arm11_gdb_dummy_fp_reg =
 {
 	"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 };
 
-u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 
 reg_t arm11_gdb_dummy_fps_reg =
 {
@@ -630,8 +630,8 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 
 		scan_field_t	chain5_fields[3];
 
-		u8			Ready		= 0;	/* ignored */
-		u8			Valid		= 0;	/* ignored */
+		uint8_t			Ready		= 0;	/* ignored */
+		uint8_t			Valid		= 0;	/* ignored */
 
 		arm11_setup_field(arm11, 32, &R(RDTR),	NULL, chain5_fields + 0);
 		arm11_setup_field(arm11,  1, &Ready,	NULL, chain5_fields + 1);
@@ -717,7 +717,7 @@ int arm11_arch_state(struct target_s *target)
 }
 
 /* target request support */
-int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
+int arm11_target_request_data(struct target_s *target, u32 size, uint8_t *buffer)
 {
 	FNC_INFO_NOTIMPLEMENTED;
 
@@ -1090,7 +1090,7 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
  * count: number of items of <size>
  */
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	/** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
 
@@ -1173,7 +1173,7 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
 	return ERROR_OK;
 }
 
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	FNC_INFO;
 
@@ -1285,7 +1285,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
 
 
 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
+int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, uint8_t *buffer)
 {
 	FNC_INFO;
 
@@ -1395,11 +1395,11 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
 	// Save regs
 	for (size_t i = 0; i < 16; i++)
 	{
-		context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
+		context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
 		LOG_DEBUG("Save %zi: 0x%x",i,context[i]);
 	}
 
-	cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
+	cpsr = buf_get_u32((uint8_t*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
 	LOG_DEBUG("Save CPSR: 0x%x", cpsr);
 
 	for (int i = 0; i < num_mem_params; i++)
@@ -1521,10 +1521,10 @@ restore:
 	{
 		LOG_DEBUG("restoring register %s with value 0x%8.8x",
 			 arm11->reg_list[i].name, context[i]);
-		arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
+		arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
 	}
 	LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
-	arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
+	arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
 
 //	arm11->core_state = core_state;
 //	arm11->core_mode = core_mode;
@@ -1668,7 +1668,7 @@ int arm11_get_reg(reg_t *reg)
 }
 
 /** Change a value in the register cache */
-int arm11_set_reg(reg_t *reg, u8 *buf)
+int arm11_set_reg(reg_t *reg, uint8_t *buf)
 {
 	FNC_INFO;
 
@@ -1730,7 +1730,7 @@ int arm11_build_reg_cache(target_t *target)
 
 		r->name				= rd->name;
 		r->size				= 32;
-		r->value			= (u8 *)(arm11->reg_values + i);
+		r->value			= (uint8_t *)(arm11->reg_values + i);
 		r->dirty			= 0;
 		r->valid			= 0;
 		r->bitfield_desc	= NULL;

src/target/arm11.h

@@ -66,7 +66,7 @@ do {														\
 typedef struct arm11_register_history_s
 {
 	u32		value;
-	u8		valid;
+	uint8_t		valid;
 }arm11_register_history_t;
 
 enum arm11_debug_version
@@ -86,7 +86,7 @@ typedef struct arm11_common_s
 
 	u32		device_id;		/**< IDCODE readout				*/
 	u32		didr;			/**< DIDR readout (debug capabilities)	*/
-	u8		implementor;	/**< DIDR Implementor readout		*/
+	uint8_t		implementor;	/**< DIDR Implementor readout		*/
 
 	size_t	brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
 	size_t	wrp;			/**< Number of Watchpoint Register Pairs from DIDR	*/
@@ -191,7 +191,7 @@ int arm11_poll(struct target_s *target);
 int arm11_arch_state(struct target_s *target);
 
 /* target request support */
-int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
+int arm11_target_request_data(struct target_s *target, u32 size, uint8_t *buffer);
 
 /* target execution control */
 int arm11_halt(struct target_s *target);
@@ -211,11 +211,11 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 * count: number of items of <size>
 */
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
 
 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
+int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, uint8_t *buffer);
 
 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 
@@ -237,7 +237,7 @@ int arm11_quit(void);
 
 /* helpers */
 int arm11_build_reg_cache(target_t *target);
-int arm11_set_reg(reg_t *reg, u8 *buf);
+int arm11_set_reg(reg_t *reg, uint8_t *buf);
 int arm11_get_reg(reg_t *reg);
 
 void arm11_record_register_history(arm11_common_t * arm11);
@@ -246,9 +246,9 @@ void arm11_dump_reg_changes(arm11_common_t * arm11);
 /* internals */
 
 void arm11_setup_field			(arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
-void arm11_add_IR				(arm11_common_t * arm11, u8 instr, tap_state_t state);
-void arm11_add_debug_SCAN_N		(arm11_common_t * arm11, u8 chain, tap_state_t state);
-void arm11_add_debug_INST		(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
+void arm11_add_IR				(arm11_common_t * arm11, uint8_t instr, tap_state_t state);
+void arm11_add_debug_SCAN_N		(arm11_common_t * arm11, uint8_t chain, tap_state_t state);
+void arm11_add_debug_INST		(arm11_common_t * arm11, u32 inst, uint8_t * flag, tap_state_t state);
 int arm11_read_DSCR				(arm11_common_t * arm11, u32 *dscr);
 int arm11_write_DSCR			(arm11_common_t * arm11, u32 dscr);
 
@@ -275,7 +275,7 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state
 typedef struct arm11_sc7_action_s
 {
 	bool	write;				/**< Access mode: true for write, false for read.	*/
-	u8		address;			/**< Register address mode. Use enum #arm11_sc7		*/
+	uint8_t		address;			/**< Register address mode. Use enum #arm11_sc7		*/
 	u32		value;				/**< If write then set this to value to be written.
 									 In read mode this receives the read value when the
 									 function returns.					*/

src/target/arm11_dbgtap.c

@@ -97,7 +97,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo
  *
  * \remarks			This adds to the JTAG command queue but does \em not execute it.
  */
-void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
+void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state)
 {
 	jtag_tap_t *tap;
 	tap = arm11->target->tap;
@@ -122,10 +122,10 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
  *  arm11_add_debug_SCAN_N().
  *
  */
-static void arm11_in_handler_SCAN_N(u8 *in_value)
+static void arm11_in_handler_SCAN_N(uint8_t *in_value)
 {
 	/** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */
-	u8 v = *in_value & 0x1F;
+	uint8_t v = *in_value & 0x1F;
 
 	if (v != 0x10)
 	{
@@ -160,7 +160,7 @@ static void arm11_in_handler_SCAN_N(u8 *in_value)
  * \remarks			This adds to the JTAG command queue but does \em not execute it.
  */
 
-void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
+void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
 {
 	JTAG_DEBUG("SCREG <= 0x%02x", chain);
 
@@ -168,7 +168,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
 
 	scan_field_t		field;
 
-	u8 tmp[1];
+	uint8_t tmp[1];
 	arm11_setup_field(arm11, 5, &chain, &tmp, &field);
 
 	arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
@@ -195,7 +195,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
  *
  * \remarks			This adds to the JTAG command queue but does \em not execute it.
  */
-void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
+void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, uint8_t * flag, tap_state_t state)
 {
 	JTAG_DEBUG("INST <= 0x%08x", inst);
 
@@ -374,7 +374,7 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
 
 		while (1)
 		{
-			u8 flag;
+			uint8_t flag;
 
 			arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
 
@@ -426,8 +426,8 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data,
 	scan_field_t	chain5_fields[3];
 
 	u32				Data;
-	u8				Ready;
-	u8				nRetry;
+	uint8_t				Ready;
+	uint8_t				nRetry;
 
 	arm11_setup_field(arm11, 32,    &Data,  NULL,		chain5_fields + 0);
 	arm11_setup_field(arm11,  1,    NULL,   &Ready,		chain5_fields + 1);
@@ -516,8 +516,8 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 *
 	arm11_setup_field(arm11,  1,    NULL,			NULL /*&Ready*/,	chain5_fields + 1);
 	arm11_setup_field(arm11,  1,    NULL,			NULL,				chain5_fields + 2);
 
-	u8			Readies[count + 1];
-	u8	*		ReadyPos			= Readies;
+	uint8_t			Readies[count + 1];
+	uint8_t	*		ReadyPos			= Readies;
 
 	while (count--)
 	{
@@ -603,8 +603,8 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat
 	scan_field_t	chain5_fields[3];
 
 	u32			Data;
-	u8			Ready;
-	u8			nRetry;
+	uint8_t			Ready;
+	uint8_t			nRetry;
 
 	arm11_setup_field(arm11, 32,    NULL,	&Data,	    chain5_fields + 0);
 	arm11_setup_field(arm11,  1,    NULL,	&Ready,	    chain5_fields + 1);
@@ -685,12 +685,12 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c
 
 	scan_field_t	chain7_fields[3];
 
-	u8				nRW;
+	uint8_t				nRW;
 	u32				DataOut;
-	u8				AddressOut;
-	u8				Ready;
+	uint8_t				AddressOut;
+	uint8_t				Ready;
 	u32				DataIn;
-	u8				AddressIn;
+	uint8_t				AddressIn;
 
 	arm11_setup_field(arm11,  1, &nRW,			&Ready,		chain7_fields + 0);
 	arm11_setup_field(arm11, 32, &DataOut,		&DataIn,	chain7_fields + 1);

src/target/arm720t.c

@@ -43,8 +43,8 @@ int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm720t_quit(void);
 int arm720t_arch_state(struct target_s *target);
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
 int arm720t_soft_reset_halt(struct target_s *target);
 
 target_type_t arm720t_target =
@@ -91,8 +91,8 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	scan_field_t fields[2];
-	u8 out_buf[4];
-	u8 instruction_buf = instruction;
+	uint8_t out_buf[4];
+	uint8_t instruction_buf = instruction;
 
 	buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 
@@ -118,9 +118,9 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
 
 	if (in)
 	{
-		fields[1].in_value = (u8 *)in;
+		fields[1].in_value = (uint8_t *)in;
 		jtag_add_dr_scan(2, fields, jtag_get_end_state());
-		jtag_add_callback(arm7flip32, (u8 *)in);
+		jtag_add_callback(arm7flip32, (uint8_t *)in);
 	} else
 	{
 		jtag_add_dr_scan(2, fields, jtag_get_end_state());
@@ -329,7 +329,7 @@ int arm720t_arch_state(struct target_s *target)
 	return ERROR_OK;
 }
 
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -349,7 +349,7 @@ int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun
 	return retval;
 }
 
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	int retval;
 

src/target/arm7_9_common.c

@@ -373,7 +373,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		{
 			u32 current_instr;
 			/* check that user program as not modified breakpoint instruction */
-			if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
+			if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -387,7 +387,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		{
 			u16 current_instr;
 			/* check that user program as not modified breakpoint instruction */
-			if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
+			if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -739,7 +739,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 {
 	static int set=0;
-	static u8 check_value[4], check_mask[4];
+	static uint8_t check_value[4], check_mask[4];
 
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -781,7 +781,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
  * @param buffer Pointer to the buffer that will hold the data
  * @return The result of receiving data from the Embedded ICE unit
  */
-int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
+int arm7_9_target_request_data(target_t *target, u32 size, uint8_t *buffer)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2208,7 +2208,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
 	return jtag_execute_queue();
 }
 
-int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2384,7 +2384,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 	return ERROR_OK;
 }
 
-int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2568,7 +2568,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 }
 
 static int dcc_count;
-static u8 *dcc_buffer;
+static uint8_t *dcc_buffer;
 
 static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
 {
@@ -2581,7 +2581,7 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
 
 	int little=target->endianness==TARGET_LITTLE_ENDIAN;
 	int count=dcc_count;
-	u8 *buffer=dcc_buffer;
+	uint8_t *buffer=dcc_buffer;
 	if (count>2)
 	{
 		/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
@@ -2590,7 +2590,7 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
 		buffer+=4;
 
 		embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
-		u8 reg_addr = ice_reg->addr & 0x1f;
+		uint8_t reg_addr = ice_reg->addr & 0x1f;
 		jtag_tap_t *tap;
 		tap = ice_reg->jtag_info->tap;
 
@@ -2623,7 +2623,7 @@ static const u32 dcc_code[] =
 
 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
 
-int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
+int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2636,7 +2636,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 	/* regrab previously allocated working_area, or allocate a new one */
 	if (!arm7_9->dcc_working_area)
 	{
-		u8 dcc_code_buf[6 * 4];
+		uint8_t dcc_code_buf[6 * 4];
 
 		/* make sure we have a working area */
 		if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)

src/target/arm7_9_common.h

@@ -80,7 +80,7 @@ typedef struct arm7_9_common_s
 	void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
 
 	void (*write_xpsr)(target_t *target, u32 xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
-	void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
+	void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
 	void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
 
 	void (*load_word_regs)(target_t *target, u32 mask);
@@ -115,7 +115,7 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx);
 
 int arm7_9_poll(target_t *target);
 
-int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer);
+int arm7_9_target_request_data(target_t *target, u32 size, uint8_t *buffer);
 
 int arm7_9_setup(target_t *target);
 int arm7_9_assert_reset(target_t *target);
@@ -131,9 +131,9 @@ int arm7_9_restore_context(target_t *target);
 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
-int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
+int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer);
 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
 

src/target/arm7tdmi.c

@@ -95,8 +95,8 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 			&& (target->debug_reason != DBG_REASON_SINGLESTEP))
 	{
 		scan_field_t fields[2];
-		u8 databus[4];
-		u8 breakpoint;
+		uint8_t databus[4];
+		uint8_t breakpoint;
 
 		jtag_set_end_state(TAP_DRPAUSE);
 
@@ -185,11 +185,11 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
-	fields[1].in_value = (u8 *)in;
+	fields[1].in_value = (uint8_t *)in;
 
 	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
-	jtag_add_callback(arm7flip32, (u8 *)in);
+	jtag_add_callback(arm7flip32, (uint8_t *)in);
 
 	jtag_add_runtest(0, jtag_get_end_state());
 
@@ -214,7 +214,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	return ERROR_OK;
 }
 
-void arm_endianness(u8 *tmp, void *in, int size, int be, int flip)
+void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
 {
 	u32 readback=le_to_h_u32(tmp);
 	if (flip)
@@ -224,30 +224,30 @@ void arm_endianness(u8 *tmp, void *in, int size, int be, int flip)
 		case 4:
 			if (be)
 			{
-				h_u32_to_be(((u8*)in), readback);
+				h_u32_to_be(((uint8_t*)in), readback);
 			} else
 			{
-				 h_u32_to_le(((u8*)in), readback);
+				 h_u32_to_le(((uint8_t*)in), readback);
 			}
 			break;
 		case 2:
 			if (be)
 			{
-				h_u16_to_be(((u8*)in), readback & 0xffff);
+				h_u16_to_be(((uint8_t*)in), readback & 0xffff);
 			} else
 			{
-				h_u16_to_le(((u8*)in), readback & 0xffff);
+				h_u16_to_le(((uint8_t*)in), readback & 0xffff);
 			}
 			break;
 		case 1:
-			*((u8 *)in)= readback & 0xff;
+			*((uint8_t *)in)= readback & 0xff;
 			break;
 	}
 }
 
-static int arm7endianness(u8 *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
+static int arm7endianness(uint8_t *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
 {
-	arm_endianness((u8 *)captured, in, (int)size, (int)be, 1);
+	arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1);
 	return ERROR_OK;
 }
 
@@ -397,7 +397,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 	int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 	u32 *buf_u32 = buffer;
 	u16 *buf_u16 = buffer;
-	u8 *buf_u8 = buffer;
+	uint8_t *buf_u8 = buffer;
 
 	/* STMIA r0-15, [r0] at debug speed
 	 * register values will start to appear on 4th DCLK
@@ -481,7 +481,7 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 }
 
-void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
+void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;

src/target/arm920t.c

@@ -48,8 +48,8 @@ int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm920t_quit(void);
 int arm920t_arch_state(struct target_s *target);
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
 int arm920t_soft_reset_halt(struct target_s *target);
 
 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
@@ -99,9 +99,9 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	scan_field_t fields[4];
-	u8 access_type_buf = 1;
-	u8 reg_addr_buf = reg_addr & 0x3f;
-	u8 nr_w_buf = 0;
+	uint8_t access_type_buf = 1;
+	uint8_t reg_addr_buf = reg_addr & 0x3f;
+	uint8_t nr_w_buf = 0;
 
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0xf);
@@ -129,11 +129,11 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
 
 	jtag_add_dr_scan(4, fields, jtag_get_end_state());
 
-	fields[1].in_value = (u8 *)value;
+	fields[1].in_value = (uint8_t *)value;
 
 	jtag_add_dr_scan(4, fields, jtag_get_end_state());
 
-	jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
+	jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value);
 
 	#ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	jtag_execute_queue();
@@ -149,10 +149,10 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	scan_field_t fields[4];
-	u8 access_type_buf = 1;
-	u8 reg_addr_buf = reg_addr & 0x3f;
-	u8 nr_w_buf = 1;
-	u8 value_buf[4];
+	uint8_t access_type_buf = 1;
+	uint8_t reg_addr_buf = reg_addr & 0x3f;
+	uint8_t nr_w_buf = 1;
+	uint8_t value_buf[4];
 
 	buf_set_u32(value_buf, 0, 32, value);
 
@@ -196,10 +196,10 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	scan_field_t fields[4];
-	u8 access_type_buf = 0;		/* interpreted access */
-	u8 reg_addr_buf = 0x0;
-	u8 nr_w_buf = 0;
-	u8 cp15_opcode_buf[4];
+	uint8_t access_type_buf = 0;		/* interpreted access */
+	uint8_t reg_addr_buf = 0x0;
+	uint8_t nr_w_buf = 0;
+	uint8_t cp15_opcode_buf[4];
 
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0xf);
@@ -518,7 +518,7 @@ int arm920t_arch_state(struct target_s *target)
 	return ERROR_OK;
 }
 
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	int retval;
 
@@ -527,7 +527,7 @@ int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun
 	return retval;
 }
 
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;

src/target/arm926ejs.c

@@ -45,7 +45,7 @@ int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *c
 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm926ejs_quit(void);
-int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
 
 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
 static int arm926ejs_mmu(struct target_s *target, int *enabled);
@@ -91,15 +91,15 @@ target_type_t arm926ejs_target =
 	.mmu = arm926ejs_mmu
 };
 
-int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
+int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
 {
 	/* FIX!!!! this code should be reenabled. For now it does not check
 	 * the queue...*/
 	return 0;
 #if 0
 	/* The ARM926EJ-S' instruction register is 4 bits wide */
-	u8 t = *captured & 0xf;
-	u8 t2 = *field->in_check_value & 0xf;
+	uint8_t t = *captured & 0xf;
+	uint8_t t2 = *field->in_check_value & 0xf;
 	if (t == t2)
 	{
 		return ERROR_OK;
@@ -123,9 +123,9 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 	scan_field_t fields[4];
-	u8 address_buf[2];
-	u8 nr_w_buf = 0;
-	u8 access = 1;
+	uint8_t address_buf[2];
+	uint8_t nr_w_buf = 0;
+	uint8_t access = 1;
 
 	buf_set_u32(address_buf, 0, 14, address);
 
@@ -139,7 +139,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-	fields[0].in_value = (u8 *)value;
+	fields[0].in_value = (uint8_t *)value;
 
 
 	fields[1].tap = jtag_info->tap;
@@ -167,7 +167,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 		nr_w_buf = 0;
 		jtag_add_dr_scan(4, fields, jtag_get_end_state());
 
-		jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
+		jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value);
 
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
@@ -192,10 +192,10 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 	scan_field_t fields[4];
-	u8 value_buf[4];
-	u8 address_buf[2];
-	u8 nr_w_buf = 1;
-	u8 access = 1;
+	uint8_t value_buf[4];
+	uint8_t address_buf[2];
+	uint8_t nr_w_buf = 1;
+	uint8_t access = 1;
 
 	buf_set_u32(address_buf, 0, 14, address);
 	buf_set_u32(value_buf, 0, 32, value);
@@ -625,7 +625,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 }
 
-int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;

src/target/arm926ejs.h

@@ -41,7 +41,7 @@ typedef struct arm926ejs_common_s
 extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap);
 extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx); 
 extern int arm926ejs_arch_state(struct target_s *target); 
-extern int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); 
+extern int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); 
 extern int arm926ejs_soft_reset_halt(struct target_s *target);
 
 #endif /* ARM926EJS_H */

src/target/arm966e.c

@@ -164,8 +164,8 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	scan_field_t fields[3];
-	u8 reg_addr_buf = reg_addr & 0x3f;
-	u8 nr_w_buf = 0;
+	uint8_t reg_addr_buf = reg_addr & 0x3f;
+	uint8_t nr_w_buf = 0;
 
 	jtag_set_end_state(TAP_IDLE);
 	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
@@ -191,11 +191,11 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
 
 	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
-	fields[1].in_value = (u8 *)value;
+	fields[1].in_value = (uint8_t *)value;
 
 	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
-	jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
+	jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value);
 
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
@@ -216,9 +216,9 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	scan_field_t fields[3];
-	u8 reg_addr_buf = reg_addr & 0x3f;
-	u8 nr_w_buf = 1;
-	u8 value_buf[4];
+	uint8_t reg_addr_buf = reg_addr & 0x3f;
+	uint8_t nr_w_buf = 1;
+	uint8_t value_buf[4];
 
 	buf_set_u32(value_buf, 0, 32, value);
 

src/target/arm9tdmi.c

@@ -107,9 +107,9 @@ int arm9tdmi_examine_debug_reason(target_t *target)
 			&& (target->debug_reason != DBG_REASON_SINGLESTEP))
 	{
 		scan_field_t fields[3];
-		u8 databus[4];
-		u8 instructionbus[4];
-		u8 debug_reason;
+		uint8_t databus[4];
+		uint8_t instructionbus[4];
+		uint8_t debug_reason;
 
 		jtag_set_end_state(TAP_DRPAUSE);
 
@@ -166,9 +166,9 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 {
 	int retval = ERROR_OK;
 	scan_field_t fields[3];
-	u8 out_buf[4];
-	u8 instr_buf[4];
-	u8 sysspeed_buf = 0x0;
+	uint8_t out_buf[4];
+	uint8_t instr_buf[4];
+	uint8_t sysspeed_buf = 0x0;
 
 	/* prepare buffer */
 	buf_set_u32(out_buf, 0, 32, out);
@@ -203,10 +203,10 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 
 	if (in)
 	{
-		fields[0].in_value=(u8 *)in;
+		fields[0].in_value=(uint8_t *)in;
 		jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
-		jtag_add_callback(arm_le_to_h_u32, (u8 *)in);
+		jtag_add_callback(arm_le_to_h_u32, (uint8_t *)in);
 	}
 	else
 	{
@@ -251,7 +251,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-	fields[0].in_value = (u8 *)in;
+	fields[0].in_value = (uint8_t *)in;
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 3;
@@ -265,7 +265,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 
 	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
-	jtag_add_callback(arm_le_to_h_u32, (u8 *)in);
+	jtag_add_callback(arm_le_to_h_u32, (uint8_t *)in);
 
 	jtag_add_runtest(0, jtag_get_end_state());
 
@@ -290,11 +290,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	return ERROR_OK;
 }
 
-extern void arm_endianness(u8 *tmp, void *in, int size, int be, int flip);
+extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
 
-static int arm9endianness(u8 *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
+static int arm9endianness(uint8_t *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
 {
-	arm_endianness((u8 *)captured, in, (int)size, (int)be, 0);
+	arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0);
 	return ERROR_OK;
 }
 
@@ -448,7 +448,7 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 	int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 	u32 *buf_u32 = buffer;
 	u16 *buf_u16 = buffer;
-	u8 *buf_u8 = buffer;
+	uint8_t *buf_u8 = buffer;
 
 	/* STMIA r0-15, [r0] at debug speed
 	 * register values will start to appear on 4th DCLK
@@ -539,7 +539,7 @@ void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
+void arm9tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;

src/target/arm_adi_v5.c

@@ -70,12 +70,12 @@ static u32 max_tar_block_size(u32 tar_autoincr_block, u32 address)
  *                                                                         *
 ***************************************************************************/
 
-/* Scan out and in from target ordered u8 buffers */
-int adi_jtag_dp_scan(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
+/* Scan out and in from target ordered uint8_t buffers */
+int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 {
 	arm_jtag_t *jtag_info = swjdp->jtag_info;
 	scan_field_t fields[2];
-	u8 out_addr_buf;
+	uint8_t out_addr_buf;
 
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, instr, NULL);
@@ -101,12 +101,12 @@ int adi_jtag_dp_scan(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *o
 }
 
 /* Scan out and in from host ordered u32 variables */
-int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
+int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, u32 outvalue, u32 *invalue, uint8_t *ack)
 {
 	arm_jtag_t *jtag_info = swjdp->jtag_info;
 	scan_field_t fields[2];
-	u8 out_value_buf[4];
-	u8 out_addr_buf;
+	uint8_t out_value_buf[4];
+	uint8_t out_addr_buf;
 
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, instr, NULL);
@@ -129,10 +129,10 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u
 
 	if (invalue)
 	{
-		fields[1].in_value = (u8 *)invalue;
+		fields[1].in_value = (uint8_t *)invalue;
 		jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
-		jtag_add_callback(arm_le_to_h_u32, (u8 *)invalue);
+		jtag_add_callback(arm_le_to_h_u32, (uint8_t *)invalue);
 	} else
 	{
 
@@ -143,7 +143,7 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u
 }
 
 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
-int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
+int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue)
 {
 	adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 
@@ -161,7 +161,7 @@ int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *o
 	return ERROR_OK;
 }
 
-int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
+int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, u32 outvalue, u32 *invalue)
 {
 	adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 
@@ -287,17 +287,17 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
  *                                                                         *
 ***************************************************************************/
 
-int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
+int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, uint8_t reg_addr)
 {
 	return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
 }
 
-int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
+int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, uint8_t reg_addr)
 {
 	return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
 }
 
-int dap_ap_select(swjdp_common_t *swjdp,u8 apsel)
+int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel)
 {
 	u32 select;
 	select = (apsel<<24) & 0xFF000000;
@@ -328,7 +328,7 @@ int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
 	return ERROR_OK;
 }
 
-int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
+int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, uint8_t* out_value_buf)
 {
 	dap_dp_bankselect(swjdp, reg_addr);
 	scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
@@ -336,7 +336,7 @@ int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
 	return ERROR_OK;
 }
 
-int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
+int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, uint8_t *in_value_buf)
 {
 	dap_dp_bankselect(swjdp, reg_addr);
 	scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
@@ -345,7 +345,7 @@ int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
 }
 int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
 {
-	u8 out_value_buf[4];
+	uint8_t out_value_buf[4];
 
 	buf_set_u32(out_value_buf, 0, 32, value);
 	dap_dp_bankselect(swjdp, reg_addr);
@@ -442,16 +442,16 @@ int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
 
 /*****************************************************************************
 *                                                                            *
-* mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
+* mem_ap_write_buf(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address) *
 *                                                                            *
 * Write a buffer in target order (little endian)                             *
 *                                                                            *
 *****************************************************************************/
-int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 	u32 adr = address;
-	u8* pBuffer = buffer;
+	uint8_t* pBuffer = buffer;
 
 	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 
@@ -469,7 +469,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre
 
 			for (i = 0; i < 4; i++ )
 			{
-				*((u8*)pBuffer + (adr & 0x3)) = outvalue;
+				*((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 				outvalue >>= 8;
 				adr++;
 			}
@@ -516,7 +516,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre
 	return retval;
 }
 
-int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	int retval = ERROR_OK;
 	int wcount, blocksize, writecount, i;
@@ -563,7 +563,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u3
 
 				for (i = 0; i < nbytes; i++ )
 				{
-					*((u8*)buffer + (address & 0x3)) = outvalue;
+					*((uint8_t*)buffer + (address & 0x3)) = outvalue;
 					outvalue >>= 8;
 					address++;
 				}
@@ -587,7 +587,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u3
 	return retval;
 }
 
-int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	int retval = ERROR_OK;
 
@@ -612,7 +612,7 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre
 	return retval;
 }
 
-int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	int retval = ERROR_OK;
 	int wcount, blocksize, writecount, i;
@@ -655,7 +655,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
 
 				for (i = 0; i < nbytes; i++ )
 				{
-					*((u8*)buffer + (address & 0x3)) = outvalue;
+					*((uint8_t*)buffer + (address & 0x3)) = outvalue;
 					outvalue >>= 8;
 					address++;
 				}
@@ -679,7 +679,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
 	return retval;
 }
 
-int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	int retval = ERROR_OK;
 
@@ -704,16 +704,16 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
 
 /*********************************************************************************
 *                                                                                *
-* mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)  *
+* mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)  *
 *                                                                                *
 * Read block fast in target order (little endian) into a buffer                  *
 *                                                                                *
 **********************************************************************************/
-int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 	u32 adr = address;
-	u8* pBuffer = buffer;
+	uint8_t* pBuffer = buffer;
 
 	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 
@@ -772,7 +772,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
 
 			for (i = 0; i < 4; i++ )
 			{
-				*((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
+				*((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 				pBuffer++;
 				adr++;
 			}
@@ -782,7 +782,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
 	return retval;
 }
 
-int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	u32 invalue;
 	int retval = ERROR_OK;
@@ -821,7 +821,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
 
 			for (i = 0; i < nbytes; i++ )
 			{
-				*((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 				buffer++;
 				address++;
 			}
@@ -834,7 +834,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
 	return retval;
 }
 
-int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	u32 invalue, i;
 	int retval = ERROR_OK;
@@ -853,7 +853,7 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
 		{
 			for (i = 0; i < 2; i++ )
 			{
-				*((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 				buffer++;
 				address++;
 			}
@@ -877,7 +877,7 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
  * The solution is to arrange for a large out/in scan in this loop and
  * and convert data afterwards.
  */
-int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	u32 invalue;
 	int retval = ERROR_OK;
@@ -913,7 +913,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
 
 			for (i = 0; i < nbytes; i++ )
 			{
-				*((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 				buffer++;
 				address++;
 			}
@@ -926,7 +926,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
 	return retval;
 }
 
-int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
 {
 	u32 invalue;
 	int retval = ERROR_OK;
@@ -941,7 +941,7 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
 		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 		dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
 		retval = swjdp_transaction_endcheck(swjdp);
-		*((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+		*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 		count--;
 		address++;
 		buffer++;
@@ -1018,7 +1018,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
 
 	u32 dbgbase,apid;
 	int romtable_present = 0;
-	u8 mem_ap;
+	uint8_t mem_ap;
 	u32 apselold;
 
 	apselold = swjdp->apsel;

src/target/arm_adi_v5.h

@@ -94,9 +94,9 @@ typedef struct swjdp_common_s
 	u32 ap_csw_value;
 	u32 ap_tar_value;
 	/* information about current pending SWjDP-AHBAP transaction */
-	u8  trans_mode;
-	u8  trans_rw;
-	u8  ack;
+	uint8_t  trans_mode;
+	uint8_t  trans_rw;
+	uint8_t  ack;
 	/* extra tck clocks for memory bus access */
 	u32	memaccess_tck;
 	/* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
@@ -105,22 +105,22 @@ typedef struct swjdp_common_s
 } swjdp_common_t;
 
 /* Accessor function for currently selected DAP-AP number */ 
-static inline u8 dap_ap_get_select(swjdp_common_t *swjdp)
+static inline uint8_t dap_ap_get_select(swjdp_common_t *swjdp)
 {
-	return (u8)( swjdp ->apsel >> 24);
+	return (uint8_t)( swjdp ->apsel >> 24);
 }
 
 /* Internal functions used in the module, partial transactions, use with caution */
-extern int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
-/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
-extern int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
-/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr); */
+extern int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, uint8_t reg_addr);
+/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, uint8_t reg_addr); */
+extern int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, uint8_t reg_addr);
+/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, uint8_t reg_addr); */
 extern int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar);
-extern int dap_ap_select(swjdp_common_t *swjdp,u8 apsel);
+extern int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel);
 
-extern int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
+extern int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, uint8_t* out_value_buf);
 extern int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value);
-extern int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
+extern int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, uint8_t *in_value_buf);
 extern int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value);
 
 /* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
@@ -135,12 +135,12 @@ extern int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value
 extern int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
 
 /* MEM-AP memory mapped bus block transfers */
-extern int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address);
+extern int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address);
+extern int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address);
 
 /* Initialisation of the debug system, power domains and registers */
 extern int ahbap_debugport_init(swjdp_common_t *swjdp);

src/target/arm_disassembler.c

@@ -102,7 +102,7 @@ int evaluate_blx_imm(u32 opcode, u32 address, arm_instruction_t *instruction)
 
 int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 L;
+	uint8_t L;
 	u32 immediate;
 	int offset;
 	u32 target_address;
@@ -139,12 +139,12 @@ int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
 /* both normal and extended instruction space (condition field b1111) */
 int evaluate_ldc_stc_mcrr_mrrc(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 cp_num = (opcode & 0xf00) >> 8;
+	uint8_t cp_num = (opcode & 0xf00) >> 8;
 	
 	/* MCRR or MRRC */
 	if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000))
 	{
-		u8 cp_opcode, Rd, Rn, CRm;
+		uint8_t cp_opcode, Rd, Rn, CRm;
 		char *mnemonic;
 		
 		cp_opcode = (opcode & 0xf0) >> 4;
@@ -171,8 +171,8 @@ int evaluate_ldc_stc_mcrr_mrrc(u32 opcode, u32 address, arm_instruction_t *instr
 	}
 	else /* LDC or STC */
 	{
-		u8 CRd, Rn, offset;
-		u8 U, N;
+		uint8_t CRd, Rn, offset;
+		uint8_t U, N;
 		char *mnemonic;
 		char addressing_mode[32];
 		
@@ -221,7 +221,7 @@ int evaluate_cdp_mcr_mrc(u32 opcode, u32 address, arm_instruction_t *instruction
 {
 	char* cond;
 	char* mnemonic;
-	u8 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
+	uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
 	
 	cond = ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode);
 	cp_num = (opcode & 0xf00) >> 8;
@@ -268,8 +268,8 @@ int evaluate_cdp_mcr_mrc(u32 opcode, u32 address, arm_instruction_t *instruction
 /* Load/store instructions */
 int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 I, P, U, B, W, L;
-	u8 Rn, Rd;
+	uint8_t I, P, U, B, W, L;
+	uint8_t Rn, Rd;
 	char *operation; /* "LDR" or "STR" */
 	char *suffix; /* "", "B", "T", "BT" */
 	char offset[32];
@@ -351,8 +351,8 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
 	}
 	else /* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */
 	{
-		u8 shift_imm, shift;
-		u8 Rm;
+		uint8_t shift_imm, shift;
+		uint8_t Rm;
 		
 		shift_imm = (opcode & 0xf80) >> 7;
 		shift = (opcode & 0x60) >> 5;
@@ -436,8 +436,8 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
 /* Miscellaneous load/store instructions */
 int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 P, U, I, W, L, S, H;
-	u8 Rn, Rd;
+	uint8_t P, U, I, W, L, S, H;
+	uint8_t Rn, Rd;
 	char *operation; /* "LDR" or "STR" */
 	char *suffix; /* "H", "SB", "SH", "D" */
 	char offset[32];
@@ -519,7 +519,7 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
 	}
 	else /* Register offset/index (+-<Rm>) */
 	{
-		u8 Rm;
+		uint8_t Rm;
 		Rm = (opcode & 0xf);
 		snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm);
 		
@@ -563,7 +563,7 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
 /* Load/store multiples instructions */
 int evaluate_ldm_stm(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 P, U, S, W, L, Rn;
+	uint8_t P, U, S, W, L, Rn;
 	u32 register_list;
 	char *addressing_mode;
 	char *mnemonic;
@@ -656,7 +656,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
 		/* Multiply (accumulate) */
 		if ((opcode & 0x0f800000) == 0x00000000)
 		{
-			u8 Rm, Rs, Rn, Rd, S;
+			uint8_t Rm, Rs, Rn, Rd, S;
 			Rm = opcode & 0xf;
 			Rs = (opcode & 0xf00) >> 8;
 			Rn = (opcode & 0xf000) >> 12;
@@ -684,7 +684,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
 		if ((opcode & 0x0f800000) == 0x00800000)
 		{
 			char* mnemonic = NULL;
-			u8 Rm, Rs, RdHi, RdLow, S;
+			uint8_t Rm, Rs, RdHi, RdLow, S;
 			Rm = opcode & 0xf;
 			Rs = (opcode & 0xf00) >> 8;
 			RdHi = (opcode & 0xf000) >> 12;
@@ -721,7 +721,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
 		/* Swap/swap byte */
 		if ((opcode & 0x0f800000) == 0x01000000)
 		{
-			u8 Rm, Rd, Rn;
+			uint8_t Rm, Rd, Rn;
 			Rm = opcode & 0xf;
 			Rd = (opcode & 0xf000) >> 12;
 			Rn = (opcode & 0xf0000) >> 16;
@@ -752,8 +752,8 @@ int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
 		/* immediate variant */
 		if (opcode & 0x02000000)
 		{
-			u8 immediate = (opcode & 0xff);
-			u8 rotate = (opcode & 0xf00);
+			uint8_t immediate = (opcode & 0xff);
+			uint8_t rotate = (opcode & 0xf00);
 			
 			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMSR%s %s_%s%s%s%s, 0x%8.8x",
 					 address, opcode, COND(opcode), PSR,
@@ -766,7 +766,7 @@ int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
 		}
 		else /* register variant */
 		{
-			u8 Rm = opcode & 0xf;
+			uint8_t Rm = opcode & 0xf;
 			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMSR%s %s_%s%s%s%s, r%i",
 					 address, opcode, COND(opcode), PSR,
 					 (opcode & 0x10000) ? "c" : "",
@@ -780,7 +780,7 @@ int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
 	}
 	else /* Move status register to register (MRS) */
 	{
-		u8 Rd;
+		uint8_t Rd;
 		
 		instruction->type = ARM_MRS;
 		Rd = (opcode & 0x0000f000) >> 12;
@@ -804,7 +804,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 	/* BX */
 	if ((opcode & 0x006000f0) == 0x00200010)
 	{
-		u8 Rm;
+		uint8_t Rm;
 		instruction->type = ARM_BX;
 		Rm = opcode & 0xf;
 		
@@ -818,7 +818,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 	/* CLZ */
 	if ((opcode & 0x006000f0) == 0x00600010)
 	{
-		u8 Rm, Rd;
+		uint8_t Rm, Rd;
 		instruction->type = ARM_CLZ;
 		Rm = opcode & 0xf;
 		Rd = (opcode & 0xf000) >> 12;
@@ -830,7 +830,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 	/* BLX(2) */
 	if ((opcode & 0x006000f0) == 0x00200030)
 	{
-		u8 Rm;
+		uint8_t Rm;
 		instruction->type = ARM_BLX;
 		Rm = opcode & 0xf;
 		
@@ -844,7 +844,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 	/* Enhanced DSP add/subtracts */
 	if ((opcode & 0x0000000f0) == 0x00000050)
 	{
-		u8 Rm, Rd, Rn;
+		uint8_t Rm, Rd, Rn;
 		char *mnemonic = NULL;
 		Rm = opcode & 0xf;
 		Rd = (opcode & 0xf000) >> 12;
@@ -894,7 +894,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 		/* SMLA<x><y> */
 		if ((opcode & 0x00600000) == 0x00000000)
 		{
-			u8 Rd, Rm, Rs, Rn;
+			uint8_t Rd, Rm, Rs, Rn;
 			instruction->type = ARM_SMLAxy;
 			Rd = (opcode & 0xf0000) >> 16;
 			Rm = (opcode & 0xf);
@@ -909,7 +909,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 		/* SMLAL<x><y> */
 		if ((opcode & 0x00600000) == 0x00400000)
 		{
-			u8 RdLow, RdHi, Rm, Rs;
+			uint8_t RdLow, RdHi, Rm, Rs;
 			instruction->type = ARM_SMLAxy;
 			RdHi = (opcode & 0xf0000) >> 16;
 			RdLow = (opcode & 0xf000) >> 12;
@@ -924,7 +924,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 		/* SMLAW<y> */
 		if (((opcode & 0x00600000) == 0x00100000) && (x == 0))
 		{
-			u8 Rd, Rm, Rs, Rn;
+			uint8_t Rd, Rm, Rs, Rn;
 			instruction->type = ARM_SMLAWy;
 			Rd = (opcode & 0xf0000) >> 16;
 			Rm = (opcode & 0xf);
@@ -939,7 +939,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 		/* SMUL<x><y> */
 		if ((opcode & 0x00600000) == 0x00300000)
 		{
-			u8 Rd, Rm, Rs;
+			uint8_t Rd, Rm, Rs;
 			instruction->type = ARM_SMULxy;
 			Rd = (opcode & 0xf0000) >> 16;
 			Rm = (opcode & 0xf);
@@ -953,7 +953,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 		/* SMULW<y> */
 		if (((opcode & 0x00600000) == 0x00100000) && (x == 1))
 		{
-			u8 Rd, Rm, Rs;
+			uint8_t Rd, Rm, Rs;
 			instruction->type = ARM_SMULWy;
 			Rd = (opcode & 0xf0000) >> 16;
 			Rm = (opcode & 0xf);
@@ -970,7 +970,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 
 int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 I, op, S, Rn, Rd;
+	uint8_t I, op, S, Rn, Rd;
 	char *mnemonic = NULL;
 	char shifter_operand[32];
 	
@@ -1055,8 +1055,8 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
 	
 	if (I) /* immediate shifter operand (#<immediate>)*/
 	{
-		u8 immed_8 = opcode & 0xff;
-		u8 rotate_imm = (opcode & 0xf00) >> 8;
+		uint8_t immed_8 = opcode & 0xff;
+		uint8_t rotate_imm = (opcode & 0xf00) >> 8;
 		u32 immediate;
 		
 		immediate = ror(immed_8, rotate_imm * 2);
@@ -1068,13 +1068,13 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
 	}
 	else /* register-based shifter operand */
 	{
-		u8 shift, Rm;
+		uint8_t shift, Rm;
 		shift = (opcode & 0x60) >> 5;
 		Rm = (opcode & 0xf);
 		
 		if ((opcode & 0x10) != 0x10) /* Immediate shifts ("<Rm>" or "<Rm>, <shift> #<shift_immediate>") */
 		{
-			u8 shift_imm;
+			uint8_t shift_imm;
 			shift_imm = (opcode & 0xf80) >> 7;
 
 			instruction->info.data_proc.variant = 1;
@@ -1124,7 +1124,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
 		}
 		else /* Register shifts ("<Rm>, <shift> <Rs>") */
 		{
-			u8 Rs = (opcode & 0xf00) >> 8;
+			uint8_t Rs = (opcode & 0xf00) >> 8;
 			
 			instruction->info.data_proc.variant = 2;
 			instruction->info.data_proc.shifter_operand.register_shift.Rm = Rm;
@@ -1368,9 +1368,9 @@ int evaluate_b_bl_blx_thumb(u16 opcode, u32 address, arm_instruction_t *instruct
 
 int evaluate_add_sub_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 Rd = (opcode >> 0) & 0x7;
-	u8 Rn = (opcode >> 3) & 0x7;
-	u8 Rm_imm = (opcode >> 6) & 0x7;
+	uint8_t Rd = (opcode >> 0) & 0x7;
+	uint8_t Rn = (opcode >> 3) & 0x7;
+	uint8_t Rm_imm = (opcode >> 6) & 0x7;
 	u32 opc = opcode & (1<<9);
 	u32 reg_imm  = opcode & (1<<10);
 	char *mnemonic;
@@ -1410,10 +1410,10 @@ int evaluate_add_sub_thumb(u16 opcode, u32 address, arm_instruction_t *instructi
 
 int evaluate_shift_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 Rd = (opcode >> 0) & 0x7;
-	u8 Rm = (opcode >> 3) & 0x7;
-	u8 imm = (opcode >> 6) & 0x1f;
-	u8 opc = (opcode >> 11) & 0x3;
+	uint8_t Rd = (opcode >> 0) & 0x7;
+	uint8_t Rm = (opcode >> 3) & 0x7;
+	uint8_t imm = (opcode >> 6) & 0x1f;
+	uint8_t opc = (opcode >> 11) & 0x3;
 	char *mnemonic = NULL;
 	
 	switch(opc)
@@ -1454,8 +1454,8 @@ int evaluate_shift_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
 
 int evaluate_data_proc_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 imm = opcode & 0xff;
-	u8 Rd = (opcode >> 8) & 0x7;
+	uint8_t imm = opcode & 0xff;
+	uint8_t Rd = (opcode >> 8) & 0x7;
 	u32 opc = (opcode >> 11) & 0x3;
 	char *mnemonic = NULL;
 	
@@ -1495,7 +1495,7 @@ int evaluate_data_proc_imm_thumb(u16 opcode, u32 address, arm_instruction_t *ins
 
 int evaluate_data_proc_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 high_reg, op, Rm, Rd,H1,H2;
+	uint8_t high_reg, op, Rm, Rd,H1,H2;
 	char *mnemonic = NULL;
 	
 	high_reg = (opcode & 0x0400) >> 10;
@@ -1655,7 +1655,7 @@ int evaluate_data_proc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
 int evaluate_load_literal_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
 	u32 immediate;
-	u8 Rd = (opcode >> 8) & 0x7; 
+	uint8_t Rd = (opcode >> 8) & 0x7; 
 
 	instruction->type = ARM_LDR;
 	immediate = opcode & 0x000000ff;
@@ -1673,10 +1673,10 @@ int evaluate_load_literal_thumb(u16 opcode, u32 address, arm_instruction_t *inst
 
 int evaluate_load_store_reg_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
-	u8 Rd = (opcode >> 0) & 0x7; 
-	u8 Rn = (opcode >> 3) & 0x7; 
-	u8 Rm = (opcode >> 6) & 0x7; 
-	u8 opc = (opcode >> 9) & 0x7; 
+	uint8_t Rd = (opcode >> 0) & 0x7; 
+	uint8_t Rn = (opcode >> 3) & 0x7; 
+	uint8_t Rm = (opcode >> 6) & 0x7; 
+	uint8_t opc = (opcode >> 9) & 0x7; 
 	char *mnemonic = NULL;
 
 	switch(opc)
@@ -1729,8 +1729,8 @@ int evaluate_load_store_reg_thumb(u16 opcode, u32 address, arm_instruction_t *in
 int evaluate_load_store_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
 	u32 offset = (opcode >> 6) & 0x1f;
-	u8 Rd = (opcode >> 0) & 0x7; 
-	u8 Rn = (opcode >> 3) & 0x7; 
+	uint8_t Rd = (opcode >> 0) & 0x7; 
+	uint8_t Rn = (opcode >> 3) & 0x7; 
 	u32 L = opcode & (1<<11);
 	u32 B = opcode & (1<<12);
 	char *mnemonic;
@@ -1773,7 +1773,7 @@ int evaluate_load_store_imm_thumb(u16 opcode, u32 address, arm_instruction_t *in
 int evaluate_load_store_stack_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
 	u32 offset = opcode  & 0xff;
-	u8 Rd = (opcode >> 8) & 0x7; 
+	uint8_t Rd = (opcode >> 8) & 0x7; 
 	u32 L = opcode & (1<<11);
 	char *mnemonic;
 
@@ -1802,8 +1802,8 @@ int evaluate_load_store_stack_thumb(u16 opcode, u32 address, arm_instruction_t *
 int evaluate_add_sp_pc_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
 	u32 imm = opcode  & 0xff;
-	u8 Rd = (opcode >> 8) & 0x7; 
-	u8 Rn;
+	uint8_t Rd = (opcode >> 8) & 0x7; 
+	uint8_t Rn;
 	u32 SP = opcode & (1<<11);
 	char *reg_name;
 
@@ -1833,7 +1833,7 @@ int evaluate_add_sp_pc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
 int evaluate_adjust_stack_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
 	u32 imm = opcode  & 0x7f;
-	u8 opc = opcode & (1<<7);
+	uint8_t opc = opcode & (1<<7);
 	char *mnemonic;
 
 	
@@ -1874,8 +1874,8 @@ int evaluate_load_store_multiple_thumb(u16 opcode, u32 address, arm_instruction_
 	u32 reg_list = opcode  & 0xff;
 	u32 L = opcode & (1<<11);
 	u32 R = opcode & (1<<8);
-	u8 Rn = (opcode >> 8) & 7;
-	u8 addr_mode = 0 /* IA */;
+	uint8_t Rn = (opcode >> 8) & 7;
+	uint8_t addr_mode = 0 /* IA */;
 	char reg_names[40];
 	char *reg_names_p;
 	char *mnemonic;
@@ -1939,7 +1939,7 @@ int evaluate_load_store_multiple_thumb(u16 opcode, u32 address, arm_instruction_
 int evaluate_cond_branch_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
 {
 	u32 offset = opcode  & 0xff;
-	u8 cond = (opcode >> 8) & 0xf;
+	uint8_t cond = (opcode >> 8) & 0xf;
 	u32 target_address;
 
 	if (cond == 0xf)

src/target/arm_disassembler.h

@@ -132,51 +132,51 @@ union arm_shifter_operand
 		u32 immediate;
 	} immediate;
 	struct {
-		u8 Rm;
-		u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
-		u8 shift_imm;
+		uint8_t Rm;
+		uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
+		uint8_t shift_imm;
 	} immediate_shift;
 	struct {
-		u8 Rm;
-		u8 shift;
-		u8 Rs;
+		uint8_t Rm;
+		uint8_t shift;
+		uint8_t Rs;
 	} register_shift;
 };
 
 typedef struct arm_data_proc_instr_s
 {
 	int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
-	u8 S;
-	u8 Rn;
-	u8 Rd;
+	uint8_t S;
+	uint8_t Rn;
+	uint8_t Rd;
 	union arm_shifter_operand shifter_operand;
 } arm_data_proc_instr_t;
 
 typedef struct arm_load_store_instr_s
 {
-	u8 Rd;
-	u8 Rn;
-	u8 U;
+	uint8_t Rd;
+	uint8_t Rn;
+	uint8_t U;
 	int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
 	int offset_mode; /* 0: immediate, 1: (scaled) register */
 	union
 	{
 		u32 offset;
 		struct {
-			u8 Rm;
-			u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
-			u8 shift_imm;
+			uint8_t Rm;
+			uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
+			uint8_t shift_imm;
 		} reg;
 	} offset;
 } arm_load_store_instr_t;
 
 typedef struct arm_load_store_multiple_instr_s
 {
-	u8 Rn;
+	uint8_t Rn;
 	u32 register_list;
-	u8 addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
-	u8 S;
-	u8 W;
+	uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
+	uint8_t S;
+	uint8_t W;
 } arm_load_store_multiple_instr_t;
 
 typedef struct arm_instruction_s

src/target/arm_jtag.c

@@ -41,7 +41,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr,  void *no_verify_ca
 	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
 	{
 		scan_field_t field;
-		u8 t[4];
+		uint8_t t[4];
 
 		field.tap = tap;
 		field.num_bits = tap->ir_length;
@@ -116,7 +116,7 @@ int arm_jtag_setup_connection(arm_jtag_t *jtag_info)
 }
 
 /* read JTAG buffer into host-endian u32, flipping bit-order */
-int arm_jtag_buf_to_u32_flip(u8 *in_buf, void *priv, struct scan_field_s *field)