diff --git a/doc/openocd.texi b/doc/openocd.texi
index 84400fce1..24c3dfd21 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1606,7 +1606,9 @@ bits long, during Capture-IR 0x42 is loaded into the IR, and bits
 @itemize @bullet
 @item @b{-expected-id NUMBER}
 @* By default it is zero. If non-zero represents the
-expected tap ID used when the JTAG chain is examined. See below.
+expected tap ID used when the JTAG chain is examined. Repeat 
+the option as many times as required if multiple id's can be
+expected. See below. 
 @item @b{-disable}
 @item @b{-enable}
 @* By default not specified the tap is enabled. Some chips have a
diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg
index 2c3e07096..2fe178501 100644
--- a/src/target/target/stm32.cfg
+++ b/src/target/target/stm32.cfg
@@ -37,15 +37,15 @@ if { [info exists BSTAPID ] } {
   # See STM Document RM0008
   # Section 26.6.2
   # Low density devices, Rev A
-  set _BSTAPID 0x06412041
+  set _BSTAPID1 0x06412041
   # Medium density devices, Rev A
-  set _BSTAPID 0x06410041
+  set _BSTAPID2 0x06410041
   # Medium density devices, Rev B and Rev Z
-  set _BSTAPID 0x16410041
+  set _BSTAPID3 0x16410041
   # High density devices, Rev A
-  set _BSTAPID 0x06414041
+  set _BSTAPID4 0x06414041
 }   
-jtag newtap $_CHIPNAME bs  -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+jtag newtap $_CHIPNAME bs  -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
 
 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME