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@@ -1888,21 +1888,6 @@ static int cortex_a8_examine_first(struct target *target) |
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armv7a->debug_base = target->dbgbase; |
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} |
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#if 0 |
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/* |
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* FIXME: assuming omap4430 |
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* |
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* APB DBGBASE reads 0x80040000, but this points to an empty ROM table. |
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* 0x80000000 is cpu0 coresight region |
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*/ |
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if (target->coreid > 3) { |
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LOG_ERROR("cortex_a8 supports up to 4 cores"); |
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return ERROR_INVALID_ARGUMENTS; |
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} |
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armv7a->debug_base = 0x80000000 | |
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((target->coreid & 0x3) << CORTEX_A8_PADDRDBG_CPU_SHIFT); |
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#endif |
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, |
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armv7a->debug_base + CPUDBG_CPUID, &cpuid); |
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if (retval != ERROR_OK) |
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