This arg was never used and was just taken from the arm jtag code. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>tags/v0.5.0-rc1
@@ -49,11 +49,11 @@ begin_ejtag_dma_read: | |||||
/* Setup Address */ | /* Setup Address */ | ||||
v = addr; | v = addr; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Initiate DMA Read & set DSTRT */ | /* Initiate DMA Read & set DSTRT */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
@@ -64,11 +64,11 @@ begin_ejtag_dma_read: | |||||
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | ||||
/* Read Data */ | /* Read Data */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ejtag_info, data); | mips_ejtag_drscan_32(ejtag_info, data); | ||||
/* Clear DMA & Check DERR */ | /* Clear DMA & Check DERR */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = ejtag_info->ejtag_ctrl; | ejtag_ctrl = ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
if (ejtag_ctrl & EJTAG_CTRL_DERR) | if (ejtag_ctrl & EJTAG_CTRL_DERR) | ||||
@@ -95,11 +95,11 @@ begin_ejtag_dma_read_h: | |||||
/* Setup Address */ | /* Setup Address */ | ||||
v = addr; | v = addr; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Initiate DMA Read & set DSTRT */ | /* Initiate DMA Read & set DSTRT */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
@@ -110,11 +110,11 @@ begin_ejtag_dma_read_h: | |||||
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | ||||
/* Read Data */ | /* Read Data */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Clear DMA & Check DERR */ | /* Clear DMA & Check DERR */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = ejtag_info->ejtag_ctrl; | ejtag_ctrl = ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
if (ejtag_ctrl & EJTAG_CTRL_DERR) | if (ejtag_ctrl & EJTAG_CTRL_DERR) | ||||
@@ -147,11 +147,11 @@ begin_ejtag_dma_read_b: | |||||
/* Setup Address */ | /* Setup Address */ | ||||
v = addr; | v = addr; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Initiate DMA Read & set DSTRT */ | /* Initiate DMA Read & set DSTRT */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
@@ -162,11 +162,11 @@ begin_ejtag_dma_read_b: | |||||
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | ||||
/* Read Data */ | /* Read Data */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Clear DMA & Check DERR */ | /* Clear DMA & Check DERR */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = ejtag_info->ejtag_ctrl; | ejtag_ctrl = ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
if (ejtag_ctrl & EJTAG_CTRL_DERR) | if (ejtag_ctrl & EJTAG_CTRL_DERR) | ||||
@@ -209,16 +209,16 @@ begin_ejtag_dma_write: | |||||
/* Setup Address */ | /* Setup Address */ | ||||
v = addr; | v = addr; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Setup Data */ | /* Setup Data */ | ||||
v = data; | v = data; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Initiate DMA Write & set DSTRT */ | /* Initiate DMA Write & set DSTRT */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
@@ -229,7 +229,7 @@ begin_ejtag_dma_write: | |||||
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | ||||
/* Clear DMA & Check DERR */ | /* Clear DMA & Check DERR */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = ejtag_info->ejtag_ctrl; | ejtag_ctrl = ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
if (ejtag_ctrl & EJTAG_CTRL_DERR) | if (ejtag_ctrl & EJTAG_CTRL_DERR) | ||||
@@ -260,16 +260,16 @@ begin_ejtag_dma_write_h: | |||||
/* Setup Address */ | /* Setup Address */ | ||||
v = addr; | v = addr; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Setup Data */ | /* Setup Data */ | ||||
v = data; | v = data; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Initiate DMA Write & set DSTRT */ | /* Initiate DMA Write & set DSTRT */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
@@ -280,7 +280,7 @@ begin_ejtag_dma_write_h: | |||||
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | ||||
/* Clear DMA & Check DERR */ | /* Clear DMA & Check DERR */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = ejtag_info->ejtag_ctrl; | ejtag_ctrl = ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
if (ejtag_ctrl & EJTAG_CTRL_DERR) | if (ejtag_ctrl & EJTAG_CTRL_DERR) | ||||
@@ -312,16 +312,16 @@ begin_ejtag_dma_write_b: | |||||
/* Setup Address*/ | /* Setup Address*/ | ||||
v = addr; | v = addr; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Setup Data */ | /* Setup Data */ | ||||
v = data; | v = data; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ejtag_info, &v); | mips_ejtag_drscan_32(ejtag_info, &v); | ||||
/* Initiate DMA Write & set DSTRT */ | /* Initiate DMA Write & set DSTRT */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
@@ -332,7 +332,7 @@ begin_ejtag_dma_write_b: | |||||
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); | ||||
/* Clear DMA & Check DERR */ | /* Clear DMA & Check DERR */ | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = ejtag_info->ejtag_ctrl; | ejtag_ctrl = ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
if (ejtag_ctrl & EJTAG_CTRL_DERR) | if (ejtag_ctrl & EJTAG_CTRL_DERR) | ||||
@@ -96,7 +96,7 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) | |||||
while (1) | while (1) | ||||
{ | { | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
ejtag_ctrl = ejtag_info->ejtag_ctrl; | ejtag_ctrl = ejtag_info->ejtag_ctrl; | ||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
if (ejtag_ctrl & EJTAG_CTRL_PRACC) | if (ejtag_ctrl & EJTAG_CTRL_PRACC) | ||||
@@ -149,12 +149,12 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add | |||||
} | } | ||||
/* Send the data out */ | /* Send the data out */ | ||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ctx->ejtag_info, &data); | mips_ejtag_drscan_32(ctx->ejtag_info, &data); | ||||
/* Clear the access pending bit (let the processor eat!) */ | /* Clear the access pending bit (let the processor eat!) */ | ||||
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; | ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; | ||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); | |||||
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); | ||||
jtag_add_clocks(5); | jtag_add_clocks(5); | ||||
@@ -169,12 +169,12 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad | |||||
int offset; | int offset; | ||||
struct mips_ejtag *ejtag_info = ctx->ejtag_info; | struct mips_ejtag *ejtag_info = ctx->ejtag_info; | ||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ctx->ejtag_info, &data); | mips_ejtag_drscan_32(ctx->ejtag_info, &data); | ||||
/* Clear access pending bit */ | /* Clear access pending bit */ | ||||
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; | ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; | ||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); | |||||
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); | ||||
jtag_add_clocks(5); | jtag_add_clocks(5); | ||||
@@ -230,7 +230,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ | |||||
return retval; | return retval; | ||||
address = data = 0; | address = data = 0; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &address); | mips_ejtag_drscan_32(ejtag_info, &address); | ||||
/* Check for read or write */ | /* Check for read or write */ | ||||
@@ -979,12 +979,12 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are | |||||
if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) | if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) | ||||
return retval; | return retval; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); | |||||
mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]); | mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]); | ||||
/* Clear the access pending bit (let the processor eat!) */ | /* Clear the access pending bit (let the processor eat!) */ | ||||
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; | ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
} | } | ||||
@@ -993,7 +993,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are | |||||
/* next fetch to dmseg should be in FASTDATA_AREA, check */ | /* next fetch to dmseg should be in FASTDATA_AREA, check */ | ||||
address = 0; | address = 0; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &address); | mips_ejtag_drscan_32(ejtag_info, &address); | ||||
if (address != MIPS32_PRACC_FASTDATA_AREA) | if (address != MIPS32_PRACC_FASTDATA_AREA) | ||||
@@ -1001,12 +1001,12 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are | |||||
/* Send the load start address */ | /* Send the load start address */ | ||||
val = addr; | val = addr; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); | |||||
mips_ejtag_fastdata_scan(ejtag_info, 1, &val); | mips_ejtag_fastdata_scan(ejtag_info, 1, &val); | ||||
/* Send the load end address */ | /* Send the load end address */ | ||||
val = addr + (count - 1) * 4; | val = addr + (count - 1) * 4; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); | |||||
mips_ejtag_fastdata_scan(ejtag_info, 1, &val); | mips_ejtag_fastdata_scan(ejtag_info, 1, &val); | ||||
for (i = 0; i < count; i++) | for (i = 0; i < count; i++) | ||||
@@ -1026,7 +1026,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are | |||||
return retval; | return retval; | ||||
address = 0; | address = 0; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); | |||||
mips_ejtag_drscan_32(ejtag_info, &address); | mips_ejtag_drscan_32(ejtag_info, &address); | ||||
if (address != MIPS32_PRACC_TEXT) | if (address != MIPS32_PRACC_TEXT) | ||||
@@ -28,7 +28,7 @@ | |||||
#include "mips32.h" | #include "mips32.h" | ||||
#include "mips_ejtag.h" | #include "mips_ejtag.h" | ||||
int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch) | |||||
int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr) | |||||
{ | { | ||||
struct jtag_tap *tap; | struct jtag_tap *tap; | ||||
@@ -58,7 +58,7 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode) | |||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE); | |||||
field.num_bits = 32; | field.num_bits = 32; | ||||
field.out_value = NULL; | field.out_value = NULL; | ||||
@@ -80,7 +80,7 @@ int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode) | |||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE); | |||||
field.num_bits = 32; | field.num_bits = 32; | ||||
field.out_value = NULL; | field.out_value = NULL; | ||||
@@ -210,7 +210,7 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info) | |||||
{ | { | ||||
uint32_t ejtag_ctrl; | uint32_t ejtag_ctrl; | ||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
/* set debug break bit */ | /* set debug break bit */ | ||||
ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK; | ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK; | ||||
@@ -129,7 +129,7 @@ struct mips_ejtag | |||||
}; | }; | ||||
int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, | int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, | ||||
int new_instr, void *delete_me_and_submit_patch); | |||||
int new_instr); | |||||
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info); | int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info); | ||||
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info); | int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info); | ||||
int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode); | int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode); | ||||
@@ -113,7 +113,7 @@ int mips_m4k_poll(struct target *target) | |||||
/* read ejtag control reg */ | /* read ejtag control reg */ | ||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
/* clear this bit before handling polling | /* clear this bit before handling polling | ||||
@@ -125,7 +125,7 @@ int mips_m4k_poll(struct target *target) | |||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; | ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
LOG_DEBUG("Reset Detected"); | LOG_DEBUG("Reset Detected"); | ||||
} | } | ||||
@@ -136,7 +136,7 @@ int mips_m4k_poll(struct target *target) | |||||
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) | if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) | ||||
{ | { | ||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); | |||||
target->state = TARGET_HALTED; | target->state = TARGET_HALTED; | ||||
@@ -228,12 +228,12 @@ int mips_m4k_assert_reset(struct target *target) | |||||
{ | { | ||||
/* use hardware to catch reset */ | /* use hardware to catch reset */ | ||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT); | |||||
} | } | ||||
else | else | ||||
{ | { | ||||
jtag_set_end_state(TAP_IDLE); | jtag_set_end_state(TAP_IDLE); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); | |||||
} | } | ||||
if (assert_srst) | if (assert_srst) | ||||
@@ -257,21 +257,21 @@ int mips_m4k_assert_reset(struct target *target) | |||||
LOG_DEBUG("Using MTAP reset to reset processor..."); | LOG_DEBUG("Using MTAP reset to reset processor..."); | ||||
/* use microchip specific MTAP reset */ | /* use microchip specific MTAP reset */ | ||||
mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP); | |||||
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND); | |||||
mchip_cmd = MCHP_ASERT_RST; | mchip_cmd = MCHP_ASERT_RST; | ||||
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); | mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); | ||||
mchip_cmd = MCHP_DE_ASSERT_RST; | mchip_cmd = MCHP_DE_ASSERT_RST; | ||||
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); | mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); | ||||
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); | |||||
} | } | ||||
else | else | ||||
{ | { | ||||
/* use ejtag reset - not supported by all cores */ | /* use ejtag reset - not supported by all cores */ | ||||
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; | uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; | ||||
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); | LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); | ||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | ||||
} | } | ||||
} | } | ||||
@@ -933,7 +933,7 @@ int mips_m4k_examine(struct target *target) | |||||
{ | { | ||||
/* we are using a pic32mx so select ejtag port | /* we are using a pic32mx so select ejtag port | ||||
* as it is not selected by default */ | * as it is not selected by default */ | ||||
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL); | |||||
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); | |||||
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface"); | LOG_DEBUG("PIC32MX Detected - using EJTAG Interface"); | ||||
mips_m4k->is_pic32mx = true; | mips_m4k->is_pic32mx = true; | ||||
} | } | ||||