Pprogram that loads another program into memory is actually writing the D- side cache. The instructions it has loaded can't be executed until they reach the I-cache. After the instructions have been written, the loader should arrange to write back any containing D-cache line and invalidate any locations already in the I-cache. For the MIPS Architecture Release2 cores, we can use synci command that does this job. For Release1 we must use "cache" instruction.tags/v0.6.0-rc1
@@ -31,6 +31,38 @@ | |||
#define MIPS32_COMMON_MAGIC 0xB320B320 | |||
/** | |||
* Memory segments (32bit kernel mode addresses) | |||
* These are the traditional names used in the 32-bit universe. | |||
*/ | |||
#define KUSEG 0x00000000 | |||
#define KSEG0 0x80000000 | |||
#define KSEG1 0xa0000000 | |||
#define KSEG2 0xc0000000 | |||
#define KSEG3 0xe0000000 | |||
/** Returns the kernel segment base of a given address */ | |||
#define KSEGX(a) ((a) & 0xe0000000) | |||
/** CP0 CONFIG regites fields */ | |||
#define MIPS32_CONFIG0_KU_SHIFT 25 | |||
#define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT) | |||
#define MIPS32_CONFIG0_K0_SHIFT 0 | |||
#define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT) | |||
#define MIPS32_CONFIG0_K23_SHIFT 28 | |||
#define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT) | |||
#define MIPS32_CONFIG0_AR_SHIFT 10 | |||
#define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT) | |||
#define MIPS32_CONFIG1_DL_SHIFT 10 | |||
#define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT) | |||
#define MIPS32_ARCH_REL1 0x0 | |||
#define MIPS32_ARCH_REL2 0x1 | |||
/* offsets into mips32 core register cache */ | |||
enum | |||
{ | |||
@@ -95,10 +127,14 @@ struct mips32_algorithm | |||
enum mips32_isa_mode isa_mode; | |||
}; | |||
#define MIPS32_OP_ADDIU 0x21 | |||
#define MIPS32_OP_ANDI 0x0C | |||
#define MIPS32_OP_BEQ 0x04 | |||
#define MIPS32_OP_BGTZ 0x07 | |||
#define MIPS32_OP_BNE 0x05 | |||
#define MIPS32_OP_ADDI 0x08 | |||
#define MIPS32_OP_AND 0x24 | |||
#define MIPS32_OP_CACHE 0x2F | |||
#define MIPS32_OP_COP0 0x10 | |||
#define MIPS32_OP_JR 0x08 | |||
#define MIPS32_OP_LUI 0x0F | |||
@@ -109,12 +145,21 @@ struct mips32_algorithm | |||
#define MIPS32_OP_MTHI 0x11 | |||
#define MIPS32_OP_MFLO 0x12 | |||
#define MIPS32_OP_MTLO 0x13 | |||
#define MIPS32_OP_RDHWR 0x3B | |||
#define MIPS32_OP_SB 0x28 | |||
#define MIPS32_OP_SH 0x29 | |||
#define MIPS32_OP_SW 0x2B | |||
#define MIPS32_OP_ORI 0x0D | |||
#define MIPS32_OP_XOR 0x26 | |||
#define MIPS32_OP_SLTU 0x2B | |||
#define MIPS32_OP_SRL 0x03 | |||
#define MIPS32_OP_SYNCI 0x1F | |||
#define MIPS32_OP_REGIMM 0x01 | |||
#define MIPS32_OP_SDBBP 0x3F | |||
#define MIPS32_OP_SPECIAL 0x00 | |||
#define MIPS32_OP_SPECIAL2 0x07 | |||
#define MIPS32_OP_SPECIAL3 0x1F | |||
#define MIPS32_COP0_MF 0x00 | |||
#define MIPS32_COP0_MT 0x04 | |||
@@ -123,33 +168,52 @@ struct mips32_algorithm | |||
#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd)) | |||
#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr)) | |||
#define MIPS32_NOP 0 | |||
#define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val) | |||
#define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND) | |||
#define MIPS32_B(off) MIPS32_BEQ(0, 0, off) | |||
#define MIPS32_BEQ(src,tar,off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off) | |||
#define MIPS32_BNE(src,tar,off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) | |||
#define MIPS32_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR) | |||
#define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel) | |||
#define MIPS32_MTC0(gpr,cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel) | |||
#define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off) | |||
#define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off) | |||
#define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val) | |||
#define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off) | |||
#define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO) | |||
#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI) | |||
#define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO) | |||
#define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI) | |||
#define MIPS32_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val) | |||
#define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off) | |||
#define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off) | |||
#define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off) | |||
#define MIPS32_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR) | |||
#define MIPS32_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL) | |||
#define MIPS32_NOP 0 | |||
#define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val) | |||
#define MIPS32_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDIU) | |||
#define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND) | |||
#define MIPS32_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val) | |||
#define MIPS32_B(off) MIPS32_BEQ(0, 0, off) | |||
#define MIPS32_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off) | |||
#define MIPS32_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off) | |||
#define MIPS32_BNE(src,tar,off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) | |||
#define MIPS32_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off) | |||
#define MIPS32_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR) | |||
#define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel) | |||
#define MIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel) | |||
#define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off) | |||
#define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off) | |||
#define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val) | |||
#define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off) | |||
#define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO) | |||
#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI) | |||
#define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO) | |||
#define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI) | |||
#define MIPS32_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val) | |||
#define MIPS32_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR) | |||
#define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off) | |||
#define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off) | |||
#define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off) | |||
#define MIPS32_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR) | |||
#define MIPS32_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL) | |||
#define MIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU) | |||
#define MIPS32_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off) | |||
#define MIPS32_SYNC 0xF | |||
#define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */ | |||
/** | |||
* Cache operations definietions | |||
* Operation field is 5 bits long : | |||
* 1) bits 1..0 hold cache type | |||
* 2) bits 4..2 hold operation code | |||
*/ | |||
#define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2)) | |||
#define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2)) | |||
/* ejtag specific instructions */ | |||
#define MIPS32_DRET 0x4200001F | |||
#define MIPS32_SDBBP 0x7000003F | |||
#define MIPS32_SDBBP 0x7000003F /* MIPS32_J_INST(MIPS32_OP_SPECIAL2, MIPS32_OP_SDBBP) */ | |||
#define MIPS16_SDBBP 0xE801 | |||
extern const struct command_registration mips32_command_handlers[]; | |||
@@ -113,6 +113,11 @@ static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, | |||
static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, | |||
uint32_t addr, uint32_t *buf); | |||
static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, | |||
uint32_t start_addr, uint32_t end_addr); | |||
static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, | |||
uint32_t start_addr, uint32_t end_addr); | |||
static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) | |||
{ | |||
uint32_t ejtag_ctrl; | |||
@@ -663,22 +668,246 @@ int mips32_cp0_write(struct mips_ejtag *ejtag_info, | |||
return retval; | |||
} | |||
/** | |||
* \b mips32_pracc_sync_cache | |||
* | |||
* Synchronize Caches to Make Instruction Writes Effective | |||
* (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, | |||
* Document Number: MD00086, Revision 2.00, June 9, 2003) | |||
* | |||
* When the instruction stream is written, the SYNCI instruction should be used | |||
* in conjunction with other instructions to make the newly-written instructions effective. | |||
* | |||
* Explanation : | |||
* A program that loads another program into memory is actually writing the D- side cache. | |||
* The instructions it has loaded can't be executed until they reach the I-cache. | |||
* | |||
* After the instructions have been written, the loader should arrange | |||
* to write back any containing D-cache line and invalidate any locations | |||
* already in the I-cache. | |||
* | |||
* You can do that with cache instructions, but those instructions are only available in kernel mode, | |||
* and a loader writing instructions for the use of its own process need not be privileged software. | |||
* | |||
* In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, | |||
* which does the whole job for a cache-line-sized chunk of the memory you just loaded: | |||
* That is, it arranges a D-cache write-back and an I-cache invalidate. | |||
* | |||
* To employ synci at user level, you need to know the size of a cache line, | |||
* and that can be obtained with a rdhwr SYNCI_Step | |||
* from one of the standard “hardware registers”. | |||
*/ | |||
static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, | |||
uint32_t start_addr, uint32_t end_addr) | |||
{ | |||
static const uint32_t code[] = { | |||
/* start: */ | |||
MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ | |||
MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ | |||
MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), | |||
MIPS32_SW(8,0,15), /* sw $8,($15) */ | |||
MIPS32_SW(9,0,15), /* sw $9,($15) */ | |||
MIPS32_SW(10,0,15), /* sw $10,($15) */ | |||
MIPS32_SW(11,0,15), /* sw $11,($15) */ | |||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ | |||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), | |||
MIPS32_LW(9,0,8), /* Load write start_addr to $9 */ | |||
MIPS32_LW(10,4,8), /* Load write end_addr to $10 */ | |||
MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */ | |||
MIPS32_BEQ(11,0,6), /* beq $11, $0, end */ | |||
MIPS32_NOP, | |||
/* synci_loop : */ | |||
MIPS32_SYNCI(0,9), /* synci 0($9) */ | |||
MIPS32_SLTU(8,10,9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */ | |||
MIPS32_BNE(8,0,NEG16(3)), /* bne $8, $0, synci_loop */ | |||
MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */ | |||
MIPS32_SYNC, | |||
/* end: */ | |||
MIPS32_LW(11,0,15), /* lw $11,($15) */ | |||
MIPS32_LW(10,0,15), /* lw $10,($15) */ | |||
MIPS32_LW(9,0,15), /* lw $9,($15) */ | |||
MIPS32_LW(8,0,15), /* lw $8,($15) */ | |||
MIPS32_B(NEG16(24)), /* b start */ | |||
MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ | |||
}; | |||
/* TODO remove array */ | |||
uint32_t *param_in = malloc(2 * sizeof(uint32_t)); | |||
int retval; | |||
param_in[0] = start_addr; | |||
param_in[1] = end_addr; | |||
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 2, param_in, 0, NULL, 1); | |||
free(param_in); | |||
return retval; | |||
} | |||
/** | |||
* \b mips32_pracc_clean_invalidate_cache | |||
* | |||
* Writeback D$ and Invalidate I$ | |||
* so that the instructions written can be visible to CPU | |||
*/ | |||
static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, | |||
uint32_t start_addr, uint32_t end_addr) | |||
{ | |||
static const uint32_t code[] = { | |||
/* start: */ | |||
MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ | |||
MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ | |||
MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), | |||
MIPS32_SW(8,0,15), /* sw $8,($15) */ | |||
MIPS32_SW(9,0,15), /* sw $9,($15) */ | |||
MIPS32_SW(10,0,15), /* sw $10,($15) */ | |||
MIPS32_SW(11,0,15), /* sw $11,($15) */ | |||
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ | |||
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), | |||
MIPS32_LW(9,0,8), /* Load write start_addr to $9 */ | |||
MIPS32_LW(10,4,8), /* Load write end_addr to $10 */ | |||
MIPS32_LW(11,8,8), /* Load write clsiz to $11 */ | |||
/* cache_loop: */ | |||
MIPS32_SLTU(8,10,9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */ | |||
MIPS32_BGTZ(8,6), /* bgtz $8, end */ | |||
MIPS32_NOP, | |||
MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK,0,9), /* cache Hit_Writeback_D, 0($9) */ | |||
MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE,0,9), /* cache Hit_Invalidate_I, 0($9) */ | |||
MIPS32_ADDU(9,9,11), /* $9 += $11 */ | |||
MIPS32_B(NEG16(7)), /* b cache_loop */ | |||
MIPS32_NOP, | |||
/* end: */ | |||
MIPS32_LW(11,0,15), /* lw $11,($15) */ | |||
MIPS32_LW(10,0,15), /* lw $10,($15) */ | |||
MIPS32_LW(9,0,15), /* lw $9,($15) */ | |||
MIPS32_LW(8,0,15), /* lw $8,($15) */ | |||
MIPS32_B(NEG16(25)), /* b start */ | |||
MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ | |||
}; | |||
/** | |||
* Find cache line size in bytes | |||
*/ | |||
uint32_t conf; | |||
uint32_t dl, clsiz; | |||
mips32_cp0_read(ejtag_info, &conf, 16, 1); | |||
dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT; | |||
/* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... */ | |||
clsiz = 0x2 << dl; | |||
/* TODO remove array */ | |||
uint32_t *param_in = malloc(3 * sizeof(uint32_t)); | |||
int retval; | |||
param_in[0] = start_addr; | |||
param_in[1] = end_addr; | |||
param_in[2] = clsiz; | |||
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 3, param_in, 0, NULL, 1); | |||
free(param_in); | |||
return retval; | |||
} | |||
int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) | |||
{ | |||
int retval; | |||
switch (size) | |||
{ | |||
case 1: | |||
return mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf); | |||
retval = mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf); | |||
break; | |||
case 2: | |||
return mips32_pracc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); | |||
retval = mips32_pracc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); | |||
break; | |||
case 4: | |||
if (count == 1) | |||
return mips32_pracc_write_u32(ejtag_info, addr, (uint32_t*)buf); | |||
{ | |||
retval = mips32_pracc_write_u32(ejtag_info, addr, (uint32_t*)buf); | |||
} | |||
else | |||
return mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); | |||
{ | |||
retval = mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); | |||
} | |||
break; | |||
default: | |||
retval = ERROR_FAIL; | |||
} | |||
return ERROR_OK; | |||
/** | |||
* If we are in the cachable regoion and cache is activated, | |||
* we must clean D$ + invalidate I$ after we did the write, | |||
* so that changes do not continue to live only in D$, but to be | |||
* replicated in I$ also (maybe we wrote the istructions) | |||
*/ | |||
uint32_t conf = 0; | |||
int cached = 0; | |||
mips32_cp0_read(ejtag_info, &conf, 16, 0); | |||
switch (KSEGX(addr)) | |||
{ | |||
case KUSEG: | |||
cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; | |||
break; | |||
case KSEG0 : | |||
cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; | |||
break; | |||
case KSEG1: | |||
/* uncachable segment - nothing to do */ | |||
break; | |||
case KSEG2: | |||
case KSEG3: | |||
cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; | |||
break; | |||
default: | |||
/* what ? */ | |||
break; | |||
} | |||
/** | |||
* Check cachablitiy bits coherency algorithm - | |||
* is the region cacheable or uncached. | |||
* If cacheable we have to synchronize the cache | |||
*/ | |||
if (cached == 0x3) | |||
{ | |||
uint32_t start_addr, end_addr; | |||
uint32_t rel; | |||
start_addr = addr; | |||
end_addr = addr + count * size; | |||
/** select cache synchronisation mechanism based on Architecture Release */ | |||
rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; | |||
switch (rel) | |||
{ | |||
case MIPS32_ARCH_REL1 : | |||
/* MIPS32/64 Release 1 - we must use cache instruction */ | |||
mips32_pracc_clean_invalidate_cache(ejtag_info, start_addr, end_addr); | |||
break; | |||
case MIPS32_ARCH_REL2 : | |||
/* MIPS32/64 Release 2 - we can use synci instruction */ | |||
mips32_pracc_sync_cache(ejtag_info, start_addr, end_addr); | |||
break; | |||
default : | |||
/* what ? */ | |||
break; | |||
} | |||
} | |||
return retval; | |||
} | |||
static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) | |||