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@@ -1041,10 +1041,18 @@ static int cortex_m_assert_reset(struct target *target) |
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retval = ERROR_OK; |
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} else { |
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/* Use a standard Cortex-M3 software reset mechanism. |
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* We default to using VECRESET as it is supported on all current cores. |
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* We default to using VECRESET as it is supported on all current cores |
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* (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!) |
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* This has the disadvantage of not resetting the peripherals, so a |
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* reset-init event handler is needed to perform any peripheral resets. |
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*/ |
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if (!cortex_m->vectreset_supported |
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&& reset_config == CORTEX_M_RESET_VECTRESET) { |
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reset_config = CORTEX_M_RESET_SYSRESETREQ; |
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LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead."); |
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LOG_WARNING("Set 'cortex_m reset_config sysresetreq'."); |
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} |
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LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ) |
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? "SYSRESETREQ" : "VECTRESET"); |
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@@ -2027,6 +2035,9 @@ int cortex_m_examine(struct target *target) |
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} |
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LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); |
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/* VECTRESET is not supported on Cortex-M0, M0+ and M1 */ |
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cortex_m->vectreset_supported = i > 1; |
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if (i == 4) { |
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target_read_u32(target, MVFR0, &mvfr0); |
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target_read_u32(target, MVFR1, &mvfr1); |
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@@ -2418,8 +2429,14 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command) |
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if (CMD_ARGC > 0) { |
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if (strcmp(*CMD_ARGV, "sysresetreq") == 0) |
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cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ; |
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else if (strcmp(*CMD_ARGV, "vectreset") == 0) |
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cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET; |
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else if (strcmp(*CMD_ARGV, "vectreset") == 0) { |
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if (target_was_examined(target) |
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&& !cortex_m->vectreset_supported) |
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LOG_WARNING("VECTRESET is not supported on your Cortex-M core!"); |
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else |
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cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET; |
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} |
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} |
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switch (cortex_m->soft_reset_config) { |
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