Browse Source

- rename log functions to stop conflicts under win32 (wingdi)

git-svn-id: svn://svn.berlios.de/openocd/trunk@523 b42882b7-edfa-0310-969c-e2dbd0fdcd60
tags/v0.1.0
ntfreak 16 years ago
parent
commit
d47e1b8f36
72 changed files with 1507 additions and 1515 deletions
  1. +23
    -23
      src/flash/at91sam7.c
  2. +80
    -80
      src/flash/cfi.c
  3. +8
    -8
      src/flash/ecos.c
  4. +15
    -15
      src/flash/flash.c
  5. +17
    -17
      src/flash/lpc2000.c
  6. +42
    -42
      src/flash/lpc3180_nand_controller.c
  7. +25
    -25
      src/flash/nand.c
  8. +1
    -1
      src/flash/non_cfi.c
  9. +3
    -3
      src/flash/s3c2410_nand.c
  10. +4
    -4
      src/flash/s3c2440_nand.c
  11. +7
    -7
      src/flash/s3c24xx_nand.c
  12. +33
    -33
      src/flash/stellaris.c
  13. +14
    -14
      src/flash/stm32x.c
  14. +18
    -18
      src/flash/str7x.c
  15. +9
    -9
      src/flash/str9x.c
  16. +16
    -16
      src/flash/str9xpec.c
  17. +67
    -67
      src/flash/tms470.c
  18. +1
    -1
      src/helper/binarybuffer.c
  19. +1
    -1
      src/helper/command.c
  20. +1
    -1
      src/helper/configuration.c
  21. +5
    -5
      src/helper/fileio.c
  22. +5
    -5
      src/helper/log.c
  23. +32
    -33
      src/helper/log.h
  24. +9
    -9
      src/helper/options.c
  25. +0
    -2
      src/helper/replacements.h
  26. +16
    -17
      src/jtag/amt_jtagaccel.c
  27. +2
    -2
      src/jtag/at91rm9200.c
  28. +11
    -11
      src/jtag/bitbang.c
  29. +17
    -17
      src/jtag/bitq.c
  30. +2
    -2
      src/jtag/ep93xx.c
  31. +133
    -134
      src/jtag/ft2232.c
  32. +26
    -27
      src/jtag/gw16012.c
  33. +45
    -45
      src/jtag/jtag.c
  34. +15
    -16
      src/jtag/parport.c
  35. +33
    -34
      src/jtag/presto.c
  36. +20
    -20
      src/jtag/usbprog.c
  37. +9
    -9
      src/openocd.c
  38. +4
    -4
      src/pld/pld.c
  39. +2
    -2
      src/pld/virtex2.c
  40. +7
    -7
      src/pld/xilinx_bit.c
  41. +67
    -67
      src/server/gdb_server.c
  42. +11
    -11
      src/server/server.c
  43. +6
    -6
      src/server/telnet_server.c
  44. +60
    -60
      src/target/arm11.c
  45. +11
    -11
      src/target/arm11_dbgtap.c
  46. +8
    -8
      src/target/arm720t.c
  47. +91
    -91
      src/target/arm7_9_common.c
  48. +10
    -10
      src/target/arm7tdmi.c
  49. +15
    -15
      src/target/arm920t.c
  50. +22
    -22
      src/target/arm926ejs.c
  51. +4
    -4
      src/target/arm966e.c
  52. +10
    -10
      src/target/arm9tdmi.c
  53. +4
    -4
      src/target/arm_disassembler.c
  54. +5
    -5
      src/target/arm_simulator.c
  55. +20
    -20
      src/target/armv4_5.c
  56. +6
    -6
      src/target/armv4_5_mmu.c
  57. +18
    -18
      src/target/armv7m.c
  58. +14
    -14
      src/target/breakpoints.c
  59. +65
    -65
      src/target/cortex_m3.c
  60. +21
    -21
      src/target/cortex_swjdp.c
  61. +8
    -8
      src/target/embeddedice.c
  62. +13
    -13
      src/target/etb.c
  63. +19
    -19
      src/target/etm.c
  64. +2
    -2
      src/target/etm_dummy.c
  65. +8
    -8
      src/target/feroceon.c
  66. +25
    -25
      src/target/image.c
  67. +9
    -9
      src/target/oocd_trace.c
  68. +50
    -50
      src/target/target.c
  69. +5
    -5
      src/target/target_request.c
  70. +1
    -1
      src/target/trace.c
  71. +102
    -102
      src/target/xscale.c
  72. +19
    -19
      src/xsvf/xsvf.c

+ 23
- 23
src/flash/at91sam7.c View File

@@ -243,7 +243,7 @@ void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
if (at91sam7_info->mck_freq > 30000000ul)
fws = 1;

DEBUG("fmcn[%i]: %i", flashplane, fmcn);
LOG_DEBUG("fmcn[%i]: %i", flashplane, fmcn);
fmr = fmcn << 16 | fws << 8;
target_write_u32(target, MC_FMR[flashplane], fmr);
}
@@ -257,21 +257,21 @@ u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, i
while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))
{
DEBUG("status[%i]: 0x%x", flashplane, status);
LOG_DEBUG("status[%i]: 0x%x", flashplane, status);
usleep(1000);
}
DEBUG("status[%i]: 0x%x", flashplane, status);
LOG_DEBUG("status[%i]: 0x%x", flashplane, status);

if (status & 0x0C)
{
ERROR("status register: 0x%x", status);
LOG_ERROR("status register: 0x%x", status);
if (status & 0x4)
ERROR("Lock Error Bit Detected, Operation Abort");
LOG_ERROR("Lock Error Bit Detected, Operation Abort");
if (status & 0x8)
ERROR("Invalid command and/or bad keyword, Operation Abort");
LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
if (status & 0x10)
ERROR("Security Bit Set, Operation Abort");
LOG_ERROR("Security Bit Set, Operation Abort");
}
return status;
@@ -287,7 +287,7 @@ int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16

fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
target_write_u32(target, MC_FCR[flashplane], fcr);
DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);
LOG_DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);

if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
{
@@ -322,7 +322,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
if (cidr == 0)
{
WARNING("Cannot identify target as an AT91SAM");
LOG_WARNING("Cannot identify target as an AT91SAM");
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -363,7 +363,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)

DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );

/* Read main and master clock freqency register */
at91sam7_read_clock_info(bank);
@@ -384,7 +384,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
at91sam7_info->target_name = "AT91SAM7S512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 2*16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
@@ -437,7 +437,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
at91sam7_info->target_name = "AT91SAM7XC512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 2*16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
@@ -474,7 +474,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
at91sam7_info->target_name = "AT91SAM7SE512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 32;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
@@ -511,12 +511,12 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
at91sam7_info->target_name = "AT91SAM7X512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
LOG_WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 32;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 2*16*64;
DEBUG("Support for AT91SAM7X512 is experimental in this version!");
LOG_DEBUG("Support for AT91SAM7X512 is experimental in this version!");
}
if (bank->size==0x40000) /* AT91SAM7X256 */
{
@@ -556,7 +556,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
return ERROR_OK;
}
WARNING("at91sam7 flash only tested for AT91SAM7Sxx series");
LOG_WARNING("at91sam7 flash only tested for AT91SAM7Sxx series");
return ERROR_OK;
}

@@ -609,7 +609,7 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
if (argc < 6)
{
WARNING("incomplete flash_bank at91sam7 configuration");
LOG_WARNING("incomplete flash_bank at91sam7 configuration");
return ERROR_FLASH_BANK_INVALID;
}
@@ -643,7 +643,7 @@ int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
{
if ((first == 0) && (last == (at91sam7_info->num_lockbits-1)))
{
WARNING("Sector numbers based on lockbit count, probably a deprecated script");
LOG_WARNING("Sector numbers based on lockbit count, probably a deprecated script");
last = bank->num_sectors-1;
}
else return ERROR_FLASH_SECTOR_INVALID;
@@ -738,7 +738,7 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)

if (offset % dst_min_alignment)
{
WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
@@ -748,7 +748,7 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
first_page = offset/dst_min_alignment;
last_page = CEIL(offset + count, dst_min_alignment);
DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
LOG_DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
at91sam7_read_clock_info(bank);

@@ -773,7 +773,7 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
return ERROR_FLASH_OPERATION_FAILED;
}
DEBUG("Write flash plane:%i page number:%i", flashplane, pagen);
LOG_DEBUG("Write flash plane:%i page number:%i", flashplane, pagen);
}
return ERROR_OK;
@@ -914,7 +914,7 @@ int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd,

if (bank->target->state != TARGET_HALTED)
{
ERROR("target has to be halted to perform flash operation");
LOG_ERROR("target has to be halted to perform flash operation");
return ERROR_TARGET_NOT_HALTED;
}
@@ -942,7 +942,7 @@ int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd,
}

status = at91sam7_get_flash_status(bank, 0);
DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status);
LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status);
at91sam7_info->nvmbits = (status>>8)&((1<<at91sam7_info->num_nvmbits)-1);

return ERROR_OK;


+ 80
- 80
src/flash/cfi.c View File

@@ -139,7 +139,7 @@ __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
{
if (!bank->sectors)
{
ERROR("BUG: sector list not yet built");
LOG_ERROR("BUG: sector list not yet built");
exit(-1);
}
return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
@@ -253,7 +253,7 @@ void cfi_intel_clear_status_register(flash_bank_t *bank)

if (target->state != TARGET_HALTED)
{
ERROR("BUG: attempted to clear status register while target wasn't halted");
LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
exit(-1);
}

@@ -267,34 +267,34 @@ u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)

while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
{
DEBUG("status: 0x%x", status);
LOG_DEBUG("status: 0x%x", status);
usleep(1000);
}

/* mask out bit 0 (reserved) */
status = status & 0xfe;

DEBUG("status: 0x%x", status);
LOG_DEBUG("status: 0x%x", status);

if ((status & 0x80) != 0x80)
{
ERROR("timeout while waiting for WSM to become ready");
LOG_ERROR("timeout while waiting for WSM to become ready");
}
else if (status != 0x80)
{
ERROR("status register: 0x%x", status);
LOG_ERROR("status register: 0x%x", status);
if (status & 0x2)
ERROR("Block Lock-Bit Detected, Operation Abort");
LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
if (status & 0x4)
ERROR("Program suspended");
LOG_ERROR("Program suspended");
if (status & 0x8)
ERROR("Low Programming Voltage Detected, Operation Aborted");
LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
if (status & 0x10)
ERROR("Program Error / Error in Setting Lock-Bit");
LOG_ERROR("Program Error / Error in Setting Lock-Bit");
if (status & 0x20)
ERROR("Error in Block Erasure or Clear Lock-Bits");
LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
if (status & 0x40)
ERROR("Block Erase Suspended");
LOG_ERROR("Block Erase Suspended");

cfi_intel_clear_status_register(bank);
}
@@ -315,15 +315,15 @@ int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
oldstatus = cfi_get_u8(bank, 0, 0x0);
status = cfi_get_u8(bank, 0, 0x0);
if ((status ^ oldstatus) & 0x40) {
ERROR("dq5 timeout, status: 0x%x", status);
LOG_ERROR("dq5 timeout, status: 0x%x", status);
return(ERROR_FLASH_OPERATION_FAILED);
} else {
DEBUG("status: 0x%x", status);
LOG_DEBUG("status: 0x%x", status);
return(ERROR_OK);
}
}
} else {
DEBUG("status: 0x%x", status);
LOG_DEBUG("status: 0x%x", status);
return(ERROR_OK);
}

@@ -331,7 +331,7 @@ int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
usleep(1000);
} while (timeout-- > 0);

ERROR("timeout, status: 0x%x", status);
LOG_ERROR("timeout, status: 0x%x", status);

return(ERROR_FLASH_BUSY);
}
@@ -361,32 +361,32 @@ int cfi_read_intel_pri_ext(flash_bank_t *bank)
pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);

DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);

pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);

DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);

pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);

DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);

pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
if (pri_ext->num_protection_fields != 1)
{
WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
}

pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);

DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);

return ERROR_OK;
}
@@ -414,7 +414,7 @@ int cfi_read_spansion_pri_ext(flash_bank_t *bank)
pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);

DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);

pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
@@ -428,20 +428,20 @@ int cfi_read_spansion_pri_ext(flash_bank_t *bank)
pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);

DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
pri_ext->EraseSuspend, pri_ext->BlkProt);

DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);

DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);


DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
(pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
(pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);

DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);

/* default values for implementation specific workarounds */
pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
@@ -486,7 +486,7 @@ int cfi_read_atmel_pri_ext(flash_bank_t *bank)
atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);

DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);

pri_ext->major_version = atmel_pri_ext.major_version;
pri_ext->minor_version = atmel_pri_ext.minor_version;
@@ -496,7 +496,7 @@ int cfi_read_atmel_pri_ext(flash_bank_t *bank)
atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);

DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);

if (atmel_pri_ext.features & 0x02)
@@ -611,14 +611,14 @@ int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **

if (argc < 6)
{
WARNING("incomplete flash_bank cfi configuration");
LOG_WARNING("incomplete flash_bank cfi configuration");
return ERROR_FLASH_BANK_INVALID;
}

if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
|| (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
{
ERROR("chip and bus width have to specified in bytes");
LOG_ERROR("chip and bus width have to specified in bytes");
return ERROR_FLASH_BANK_INVALID;
}

@@ -677,7 +677,7 @@ int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);

ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
@@ -723,7 +723,7 @@ int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);

ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
@@ -761,7 +761,7 @@ int cfi_erase(struct flash_bank_s *bank, int first, int last)
return cfi_spansion_erase(bank, first, last);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}

@@ -788,19 +788,19 @@ int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x60, command);
DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if (set)
{
cfi_command(bank, 0x01, command);
DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
bank->sectors[i].is_protected = 1;
}
else
{
cfi_command(bank, 0xd0, command);
DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
bank->sectors[i].is_protected = 0;
}
@@ -821,7 +821,7 @@ int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)

if ((block_status & 0x1) != set)
{
ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
cfi_intel_wait_status_busy(bank, 10);
@@ -889,7 +889,7 @@ int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
cfi_intel_protect(bank, set, first, last);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}

@@ -961,7 +961,7 @@ u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
return target_buffer_get_u32(target, buf);
break;
default :
ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
return 0;
}
}
@@ -1071,7 +1071,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
target_code_size = sizeof(word_32_code);
break;
default:
ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}

@@ -1080,7 +1080,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
{
if ( target_code_size > sizeof(target_code) )
{
WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
@@ -1089,7 +1089,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
if (retval != ERROR_OK)
{
WARNING("No working area available, can't do block memory writes");
LOG_WARNING("No working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};

@@ -1097,7 +1097,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
if (retval != ERROR_OK)
{
ERROR("Unable to write block write code to target");
LOG_ERROR("Unable to write block write code to target");
goto cleanup;
}
}
@@ -1110,7 +1110,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
buffer_size /= 2;
if (buffer_size <= 256)
{
WARNING("no large enough working area available, can't do block memory writes");
LOG_WARNING("no large enough working area available, can't do block memory writes");
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
goto cleanup;
}
@@ -1130,7 +1130,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
busy_pattern_val = cfi_command_val(bank, 0x80);
error_pattern_val = cfi_command_val(bank, 0x7e);

INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );

/* Programming main loop */
while (count > 0)
@@ -1148,7 +1148,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);

INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );

/* Execute algorithm, assume breakpoint for last instruction */
retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
@@ -1161,7 +1161,7 @@ int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u3
if (retval != ERROR_OK)
{
cfi_intel_clear_status_register(bank);
ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
retval = ERROR_FLASH_OPERATION_FAILED;
/* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
/* FIXME To allow fall back or recovery, we must save the actual status
@@ -1366,7 +1366,7 @@ int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address,
target_code_size = sizeof(word_32_code);
break;
default:
ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
return ERROR_FLASH_OPERATION_FAILED;
}
target_code = malloc(target_code_size);
@@ -1395,7 +1395,7 @@ int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address,
if (cfi_info->write_algorithm)
target_free_working_area(target, cfi_info->write_algorithm);

WARNING("not enough working area available, can't do block memory writes");
LOG_WARNING("not enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
};
@@ -1436,7 +1436,7 @@ int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address,

if ((retval != ERROR_OK) || status != 0x80)
{
DEBUG("status: 0x%x", status);
LOG_DEBUG("status: 0x%x", status);
exit_code = ERROR_FLASH_OPERATION_FAILED;
break;
}
@@ -1479,7 +1479,7 @@ int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);

ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}

@@ -1500,7 +1500,7 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
/* Check for valid range */
if (address & buffermask)
{
ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
}
switch(bank->chip_width)
@@ -1509,14 +1509,14 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
case 2 : bufferwsize = buffersize / 2; break;
case 1 : bufferwsize = buffersize; break;
default:
ERROR("Unsupported chip width %d", bank->chip_width);
LOG_ERROR("Unsupported chip width %d", bank->chip_width);
return ERROR_FLASH_OPERATION_FAILED;
}

/* Check for valid size */
if (wordcount > bufferwsize)
{
ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
return ERROR_FLASH_OPERATION_FAILED;
}

@@ -1531,7 +1531,7 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);

ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}

@@ -1549,7 +1549,7 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);

ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}

@@ -1579,7 +1579,7 @@ int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);

ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}

@@ -1600,7 +1600,7 @@ int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
return cfi_spansion_write_word(bank, word, address);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}

@@ -1619,10 +1619,10 @@ int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 addr
break;
case 2:
/* return cfi_spansion_write_words(bank, word, address); */
ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}

@@ -1654,7 +1654,7 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
write_p = address & ~(bank->bus_width - 1);
if ((align = address - write_p) != 0)
{
INFO("Fixup %d unaligned head bytes", align );
LOG_INFO("Fixup %d unaligned head bytes", align );

for (i = 0; i < bank->bus_width; i++)
current_word[i] = 0;
@@ -1703,7 +1703,7 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
@@ -1728,7 +1728,7 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
case 2 : bufferwsize = buffersize / 2; break;
case 1 : bufferwsize = buffersize; break;
default:
ERROR("Unsupported chip width %d", bank->chip_width);
LOG_ERROR("Unsupported chip width %d", bank->chip_width);
return ERROR_FLASH_OPERATION_FAILED;
}

@@ -1737,7 +1737,7 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
if ((write_p & 0xff) == 0)
{
INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
}
if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
{
@@ -1781,7 +1781,7 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* handle unaligned tail bytes */
if (count > 0)
{
INFO("Fixup %d unaligned tail bytes", count );
LOG_INFO("Fixup %d unaligned tail bytes", count );

copy_p = write_p;
for (i = 0; i < bank->bus_width; i++)
@@ -1828,7 +1828,7 @@ void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)

if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
{
DEBUG("swapping reversed erase region information on cmdset 0002 device");
LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");

for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
{
@@ -1929,7 +1929,7 @@ int cfi_probe(struct flash_bank_s *bank)
cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);

DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);

if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
@@ -1945,7 +1945,7 @@ int cfi_probe(struct flash_bank_s *bank)
cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);

DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);

cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
@@ -1960,14 +1960,14 @@ int cfi_probe(struct flash_bank_s *bank)
cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);

DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
(cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
(cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
(1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
@@ -1977,11 +1977,11 @@ int cfi_probe(struct flash_bank_s *bank)
cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);

DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));

if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
{
WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
}

if (cfi_info->num_erase_regions)
@@ -1990,7 +1990,7 @@ int cfi_probe(struct flash_bank_s *bank)
for (i = 0; i < cfi_info->num_erase_regions; i++)
{
cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
}
}
else
@@ -2013,7 +2013,7 @@ int cfi_probe(struct flash_bank_s *bank)
cfi_read_0002_pri_ext(bank);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}

@@ -2039,7 +2039,7 @@ int cfi_probe(struct flash_bank_s *bank)
cfi_fixup(bank, cfi_0002_fixups);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}

@@ -2118,7 +2118,7 @@ int cfi_erase_check(struct flash_bank_s *bank)
/* make sure we have a working area */
if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK)
{
WARNING("no working area available, falling back to slow memory reads");
LOG_WARNING("no working area available, falling back to slow memory reads");
}
else
{
@@ -2294,7 +2294,7 @@ int cfi_protect_check(struct flash_bank_s *bank)
return cfi_spansion_protect_check(bank);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}

@@ -2371,7 +2371,7 @@ int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
cfi_spansion_info(bank, buf, buf_size);
break;
default:
ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
}


+ 8
- 8
src/flash/ecos.c View File

@@ -147,14 +147,14 @@ int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, c
if (argc < 7)
{
WARNING("incomplete flash_bank ecosflash configuration");
LOG_WARNING("incomplete flash_bank ecosflash configuration");
return ERROR_FLASH_BANK_INVALID;
}
info = malloc(sizeof(ecosflash_flash_bank_t));
if(info == NULL)
{
ERROR("no memory for flash bank info");
LOG_ERROR("no memory for flash bank info");
exit(-1);
}
bank->driver_priv = info;
@@ -180,7 +180,7 @@ int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, c
info->target = get_target_by_num(strtoul(args[5], NULL, 0));
if (info->target == NULL)
{
ERROR("no target '%i' configured", (int)strtoul(args[5], NULL, 0));
LOG_ERROR("no target '%i' configured", (int)strtoul(args[5], NULL, 0));
exit(-1);
}
return ERROR_OK;
@@ -212,14 +212,14 @@ int loadDriver(ecosflash_flash_bank_t *info)
int retval;
if ((retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer, &buf_cnt)) != ERROR_OK)
{
ERROR("image_read_section failed with error code: %i", retval);
LOG_ERROR("image_read_section failed with error code: %i", retval);
free(buffer);
image_close(&image);
return ERROR_FLASH_BANK_INVALID;
}
target_write_buffer(target, image.sections[i].base_address, buf_cnt, buffer);
image_size += buf_cnt;
DEBUG("%u byte written at address 0x%8.8x", buf_cnt, image.sections[i].base_address);
LOG_DEBUG("%u byte written at address 0x%8.8x", buf_cnt, image.sections[i].base_address);
free(buffer);
}
@@ -266,7 +266,7 @@ int runCode(ecosflash_flash_bank_t *info,
codeStop, timeout,
&armv4_5_info)) != ERROR_OK)
{
ERROR("error executing eCos flash algorithm");
LOG_ERROR("error executing eCos flash algorithm");
return retval;
}
@@ -303,7 +303,7 @@ int eCosBoard_erase(ecosflash_flash_bank_t *info, u32 address, u32 len)
if (flashErr != 0x0)
{
ERROR("Flash erase failed with %d (%s)\n", flashErr, flash_errmsg(flashErr));
LOG_ERROR("Flash erase failed with %d (%s)\n", flashErr, flash_errmsg(flashErr));
return ERROR_JTAG_DEVICE_ERROR;
}

@@ -362,7 +362,7 @@ int eCosBoard_flash(ecosflash_flash_bank_t *info, void *data, u32 address, u32 l

if (flashErr != 0x0)
{
ERROR("Flash prog failed with %d (%s)\n", flashErr, flash_errmsg(flashErr));
LOG_ERROR("Flash prog failed with %d (%s)\n", flashErr, flash_errmsg(flashErr));
return ERROR_JTAG_DEVICE_ERROR;
}
}


+ 15
- 15
src/flash/flash.c View File

@@ -93,7 +93,7 @@ static int flash_driver_write(struct flash_bank_s *bank, u8 *buffer, u32 offset,
retval=bank->driver->write(bank, buffer, offset, count);
if (retval!=ERROR_OK)
{
ERROR("error writing to flash at address 0x%08x at offset 0x%8.8x (%d)", bank->base, offset, retval);
LOG_ERROR("error writing to flash at address 0x%08x at offset 0x%8.8x (%d)", bank->base, offset, retval);
}

return retval;
@@ -106,7 +106,7 @@ static int flash_driver_erase(struct flash_bank_s *bank, int first, int last)
retval=bank->driver->erase(bank, first, last);
if (retval!=ERROR_OK)
{
ERROR("failed erasing sectors %d to %d (%d)", first, last, retval);
LOG_ERROR("failed erasing sectors %d to %d (%d)", first, last, retval);
}

return retval;
@@ -119,7 +119,7 @@ int flash_driver_protect(struct flash_bank_s *bank, int set, int first, int last
retval=bank->driver->protect(bank, set, first, last);
if (retval!=ERROR_OK)
{
ERROR("failed setting protection for areas %d to %d (%d)", first, last, retval);
LOG_ERROR("failed setting protection for areas %d to %d (%d)", first, last, retval);
}

return retval;
@@ -177,7 +177,7 @@ flash_bank_t *get_flash_bank_by_num_noprobe(int num)
return p;
}
}
ERROR("flash bank %d does not exist", num);
LOG_ERROR("flash bank %d does not exist", num);
return NULL;
}

@@ -204,7 +204,7 @@ flash_bank_t *get_flash_bank_by_num(int num)

if (retval != ERROR_OK)
{
ERROR("auto_probe failed %d\n", retval);
LOG_ERROR("auto_probe failed %d\n", retval);
return NULL;
}
return p;
@@ -223,7 +223,7 @@ int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char

if ((target = get_target_by_num(strtoul(args[5], NULL, 0))) == NULL)
{
ERROR("target %lu not defined", strtoul(args[5], NULL, 0));
LOG_ERROR("target %lu not defined", strtoul(args[5], NULL, 0));
return ERROR_OK;
}

@@ -236,7 +236,7 @@ int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
/* register flash specific commands */
if (flash_drivers[i]->register_commands(cmd_ctx) != ERROR_OK)
{
ERROR("couldn't register '%s' commands", args[0]);
LOG_ERROR("couldn't register '%s' commands", args[0]);
exit(-1);
}

@@ -254,7 +254,7 @@ int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char

if (flash_drivers[i]->flash_bank_command(cmd_ctx, cmd, args, argc, c) != ERROR_OK)
{
ERROR("'%s' driver rejected flash bank at 0x%8.8x", args[0], c->base);
LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8x", args[0], c->base);
free(c);
return ERROR_OK;
}
@@ -279,7 +279,7 @@ int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
/* no matching flash driver found */
if (!found)
{
ERROR("flash driver '%s' not found", args[0]);
LOG_ERROR("flash driver '%s' not found", args[0]);
exit(-1);
}

@@ -356,7 +356,7 @@ int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char
retval = p->driver->info(p, buf, sizeof(buf));
command_print(cmd_ctx, "%s", buf);
if (retval != ERROR_OK)
ERROR("error retrieving flash info (%d)", retval);
LOG_ERROR("error retrieving flash info (%d)", retval);
}
}

@@ -598,7 +598,7 @@ int handle_flash_write_image_command(struct command_context_s *cmd_ctx, char *cm

if (!target)
{
ERROR("no target selected");
LOG_ERROR("no target selected");
return ERROR_OK;
}

@@ -731,14 +731,14 @@ flash_bank_t *get_flash_bank_by_addr(target_t *target, u32 addr)

if (retval != ERROR_OK)
{
ERROR("auto_probe failed %d\n", retval);
LOG_ERROR("auto_probe failed %d\n", retval);
return NULL;
}
/* check whether address belongs to this flash bank */
if ((addr >= c->base) && (addr < c->base + c->size) && target == c->target)
return c;
}
ERROR("No flash at address 0x%08x\n", addr);
LOG_ERROR("No flash at address 0x%08x\n", addr);
return NULL;
}

@@ -823,7 +823,7 @@ int flash_write(target_t *target, image_t *image, u32 *written, int erase)

if (image->sections[section].size == 0)
{
WARNING("empty section %d", section);
LOG_WARNING("empty section %d", section);
section++;
section_offset = 0;
continue;
@@ -845,7 +845,7 @@ int flash_write(target_t *target, image_t *image, u32 *written, int erase)
{
if (image->sections[section_last + 1].base_address < (run_address + run_size))
{
DEBUG("section %d out of order(very slightly surprising, but supported)", section_last + 1);
LOG_DEBUG("section %d out of order(very slightly surprising, but supported)", section_last + 1);
break;
}
if (image->sections[section_last + 1].base_address != (run_address + run_size))


+ 17
- 17
src/flash/lpc2000.c View File

@@ -146,7 +146,7 @@ int lpc2000_build_sector_list(struct flash_bank_s *bank)
}
else
{
ERROR("BUG: unknown bank->size encountered");
LOG_ERROR("BUG: unknown bank->size encountered");
exit(-1);
}
}
@@ -187,7 +187,7 @@ int lpc2000_build_sector_list(struct flash_bank_s *bank)
num_sectors = 27;
break;
default:
ERROR("BUG: unknown bank->size encountered");
LOG_ERROR("BUG: unknown bank->size encountered");
exit(-1);
break;
}
@@ -225,7 +225,7 @@ int lpc2000_build_sector_list(struct flash_bank_s *bank)
}
else
{
ERROR("BUG: unknown lpc2000_info->variant encountered");
LOG_ERROR("BUG: unknown lpc2000_info->variant encountered");
exit(-1);
}
@@ -256,7 +256,7 @@ int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 resul
/* make sure we have a working area */
if (target_alloc_working_area(target, 172, &lpc2000_info->iap_working_area) != ERROR_OK)
{
ERROR("no working area specified, can't write LPC2000 internal flash");
LOG_ERROR("no working area specified, can't write LPC2000 internal flash");
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -351,7 +351,7 @@ int lpc2000_iap_blank_check(struct flash_bank_s *bank, int first, int last)
return ERROR_FLASH_BUSY;
break;
default:
ERROR("BUG: unknown LPC2000 status code");
LOG_ERROR("BUG: unknown LPC2000 status code");
exit(-1);
}
}
@@ -367,7 +367,7 @@ int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, cha
if (argc < 8)
{
WARNING("incomplete flash_bank lpc2000 configuration");
LOG_WARNING("incomplete flash_bank lpc2000 configuration");
return ERROR_FLASH_BANK_INVALID;
}
@@ -390,7 +390,7 @@ int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, cha
}
else
{
ERROR("unknown LPC2000 variant");
LOG_ERROR("unknown LPC2000 variant");
free(lpc2000_info);
return ERROR_FLASH_BANK_INVALID;
}
@@ -437,7 +437,7 @@ int lpc2000_erase(struct flash_bank_s *bank, int first, int last)
return ERROR_FLASH_SECTOR_INVALID;
break;
default:
WARNING("lpc2000 prepare sectors returned %i", status_code);
LOG_WARNING("lpc2000 prepare sectors returned %i", status_code);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -453,7 +453,7 @@ int lpc2000_erase(struct flash_bank_s *bank, int first, int last)
return ERROR_FLASH_SECTOR_INVALID;
break;
default:
WARNING("lpc2000 erase sectors returned %i", status_code);
LOG_WARNING("lpc2000 erase sectors returned %i", status_code);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -489,7 +489,7 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* allocate a working area */
if (target_alloc_working_area(target, lpc2000_info->cmd51_max_buffer, &download_area) != ERROR_OK)
{
ERROR("no working area specified, can't write LPC2000 internal flash");
LOG_ERROR("no working area specified, can't write LPC2000 internal flash");
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -503,7 +503,7 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
if (offset % dst_min_alignment)
{
WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
@@ -515,7 +515,7 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
last_sector = i;
}
DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector);
LOG_DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector);

/* check if exception vectors should be flashed */
if ((offset == 0) && (count >= 0x20) && lpc2000_info->calc_checksum)
@@ -524,12 +524,12 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
int i = 0;
for (i = 0; i < 8; i++)
{
DEBUG("0x%2.2x: 0x%8.8x", i * 4, buf_get_u32(buffer + (i * 4), 0, 32));
LOG_DEBUG("0x%2.2x: 0x%8.8x", i * 4, buf_get_u32(buffer + (i * 4), 0, 32));
if (i != 5)
checksum += buf_get_u32(buffer + (i * 4), 0, 32);
}
checksum = 0 - checksum;
DEBUG("checksum: 0x%8.8x", checksum);
LOG_DEBUG("checksum: 0x%8.8x", checksum);
buf_set_u32(buffer + 0x14, 0, 32, checksum);
}
@@ -559,7 +559,7 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
return ERROR_FLASH_SECTOR_INVALID;
break;
default:
WARNING("lpc2000 prepare sectors returned %i", status_code);
LOG_WARNING("lpc2000 prepare sectors returned %i", status_code);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -582,7 +582,7 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
free(last_buffer);
}
DEBUG("writing 0x%x bytes to address 0x%x", thisrun_bytes, bank->base + offset + bytes_written);
LOG_DEBUG("writing 0x%x bytes to address 0x%x", thisrun_bytes, bank->base + offset + bytes_written);
/* Write data */
param_table[0] = bank->base + offset + bytes_written;
@@ -600,7 +600,7 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
return ERROR_FLASH_SECTOR_INVALID;
break;
default:
WARNING("lpc2000 returned %i", status_code);
LOG_WARNING("lpc2000 returned %i", status_code);
return ERROR_FLASH_OPERATION_FAILED;
}


+ 42
- 42
src/flash/lpc3180_nand_controller.c View File

@@ -72,7 +72,7 @@ int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, ch
if (argc < 3)
{
WARNING("incomplete 'lpc3180' nand flash configuration");
LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
return ERROR_FLASH_BANK_INVALID;
}
@@ -82,14 +82,14 @@ int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, ch
lpc3180_info->target = get_target_by_num(strtoul(args[1], NULL, 0));
if (!lpc3180_info->target)
{
ERROR("no target '%s' configured", args[1]);
LOG_ERROR("no target '%s' configured", args[1]);
return ERROR_NAND_DEVICE_INVALID;
}

lpc3180_info->osc_freq = strtoul(args[2], NULL, 0);
if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
{
WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
}
lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
lpc3180_info->sw_write_protection = 0;
@@ -119,7 +119,7 @@ int lpc3180_pll(int fclkin, u32 pll_ctrl)
int lock = (pll_ctrl & 0x1);

if (!lock)
WARNING("PLL is not locked");
LOG_WARNING("PLL is not locked");
if (!bypass && direct) /* direct mode */
return (m * fclkin) / n;
@@ -179,7 +179,7 @@ float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
}
}
DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
cycle = (1.0 / hclk) * 1000000.0;
@@ -196,14 +196,14 @@ int lpc3180_init(struct nand_device_s *device)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
/* sanitize arguments */
if ((bus_width != 8) && (bus_width != 16))
{
ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
@@ -212,7 +212,7 @@ int lpc3180_init(struct nand_device_s *device)
*/
if (bus_width == 16)
{
WARNING("LPC3180 only supports 8 bit bus width");
LOG_WARNING("LPC3180 only supports 8 bit bus width");
}
/* inform calling code about selected bus width */
@@ -220,20 +220,20 @@ int lpc3180_init(struct nand_device_s *device)
if ((address_cycles != 3) && (address_cycles != 4))
{
ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
if ((page_size != 512) && (page_size != 2048))
{
ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
/* select MLC controller if none is currently selected */
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
}
@@ -323,13 +323,13 @@ int lpc3180_reset(struct nand_device_s *device)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
ERROR("BUG: no LPC3180 NAND flash controller selected");
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
@@ -339,7 +339,7 @@ int lpc3180_reset(struct nand_device_s *device)

if (!lpc3180_controller_ready(device, 100))
{
ERROR("LPC3180 NAND controller timed out after reset");
LOG_ERROR("LPC3180 NAND controller timed out after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
}
@@ -350,7 +350,7 @@ int lpc3180_reset(struct nand_device_s *device)
if (!lpc3180_controller_ready(device, 100))
{
ERROR("LPC3180 NAND controller timed out after reset");
LOG_ERROR("LPC3180 NAND controller timed out after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
}
@@ -365,13 +365,13 @@ int lpc3180_command(struct nand_device_s *device, u8 command)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
ERROR("BUG: no LPC3180 NAND flash controller selected");
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
@@ -395,13 +395,13 @@ int lpc3180_address(struct nand_device_s *device, u8 address)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
ERROR("BUG: no LPC3180 NAND flash controller selected");
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
@@ -425,13 +425,13 @@ int lpc3180_write_data(struct nand_device_s *device, u16 data)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
ERROR("BUG: no LPC3180 NAND flash controller selected");
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
@@ -455,13 +455,13 @@ int lpc3180_read_data(struct nand_device_s *device, void *data)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
ERROR("BUG: no LPC3180 NAND flash controller selected");
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
@@ -479,7 +479,7 @@ int lpc3180_read_data(struct nand_device_s *device, void *data)
}
else
{
ERROR("BUG: bus_width neither 8 nor 16 bit");
LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
return ERROR_NAND_OPERATION_FAILED;
}
}
@@ -502,7 +502,7 @@ int lpc3180_read_data(struct nand_device_s *device, void *data)
}
else
{
ERROR("BUG: bus_width neither 8 nor 16 bit");
LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
return ERROR_NAND_OPERATION_FAILED;
}
}
@@ -519,13 +519,13 @@ int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 dat
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
ERROR("BUG: no LPC3180 NAND flash controller selected");
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
@@ -536,19 +536,19 @@ int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 dat
if (!data && oob)
{
ERROR("LPC3180 MLC controller can't write OOB data only");
LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
if (oob && (oob_size > 6))
{
ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
if (data_size > device->page_size)
{
ERROR("data size exceeds page size");
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
@@ -618,7 +618,7 @@ int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 dat
if (!lpc3180_controller_ready(device, 1000))
{
ERROR("timeout while waiting for completion of auto encode cycle");
LOG_ERROR("timeout while waiting for completion of auto encode cycle");
return ERROR_NAND_OPERATION_FAILED;
}
}
@@ -628,13 +628,13 @@ int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 dat
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
{
ERROR("couldn't read status");
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
if (status & NAND_STATUS_FAIL)
{
ERROR("write operation didn't pass, status: 0x%2.2x", status);
LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
return ERROR_NAND_OPERATION_FAILED;
}
@@ -656,13 +656,13 @@ int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
ERROR("BUG: no LPC3180 NAND flash controller selected");
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
@@ -676,14 +676,14 @@ int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data
#if 0
if (oob && (oob_size > 6))
{
ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
#endif
if (data_size > device->page_size)
{
ERROR("data size exceeds page size");
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
@@ -748,7 +748,7 @@ int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data
if (!lpc3180_controller_ready(device, 1000))
{
ERROR("timeout while waiting for completion of auto decode cycle");
LOG_ERROR("timeout while waiting for completion of auto decode cycle");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -758,11 +758,11 @@ int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data
{
if (mlc_isr & 0x40)
{
ERROR("uncorrectable error detected: 0x%2.2x", mlc_isr);
LOG_ERROR("uncorrectable error detected: 0x%2.2x", mlc_isr);
return ERROR_NAND_OPERATION_FAILED;
}
WARNING("%i symbol error detected and corrected", ((mlc_isr & 0x30) >> 4) + 1);
LOG_WARNING("%i symbol error detected and corrected", ((mlc_isr & 0x30) >> 4) + 1);
}
if (data)
@@ -804,7 +804,7 @@ int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -837,7 +837,7 @@ int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
if (target->state != TARGET_HALTED)
{
ERROR("target must be halted to use LPC3180 NAND flash controller");
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}


+ 25
- 25
src/flash/nand.c View File

@@ -193,7 +193,7 @@ int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, cha
if (argc < 1)
{
WARNING("incomplete flash device nand configuration");
LOG_WARNING("incomplete flash device nand configuration");
return ERROR_FLASH_BANK_INVALID;
}
@@ -206,7 +206,7 @@ int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, cha
/* register flash specific commands */
if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
{
ERROR("couldn't register '%s' commands", args[0]);
LOG_ERROR("couldn't register '%s' commands", args[0]);
exit(-1);
}
@@ -224,7 +224,7 @@ int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, cha

if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
{
ERROR("'%s' driver rejected nand flash", c->controller->name);
LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
free(c);
return ERROR_OK;
}
@@ -249,11 +249,11 @@ int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, cha
/* no valid NAND controller was found (i.e. the configuration option,
* didn't match one of the compiled-in controllers)
*/
ERROR("No valid NAND flash controller found (%s)", args[0]);
ERROR("compiled-in NAND flash controllers:");
LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
LOG_ERROR("compiled-in NAND flash controllers:");
for (i = 0; nand_flash_controllers[i]; i++)
{
ERROR("%i: %s", i, nand_flash_controllers[i]->name);
LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
}
return ERROR_OK;
@@ -333,7 +333,7 @@ int nand_build_bbt(struct nand_device_s *device, int first, int last)
|| (((device->page_size == 512) && (oob[5] != 0xff)) ||
((device->page_size == 2048) && (oob[0] != 0xff))))
{
WARNING("invalid block: %i", i);
LOG_WARNING("invalid block: %i", i);
device->blocks[i].is_bad = 1;
}
else
@@ -395,13 +395,13 @@ int nand_probe(struct nand_device_s *device)
switch (retval)
{
case ERROR_NAND_OPERATION_FAILED:
DEBUG("controller initialization failed");
LOG_DEBUG("controller initialization failed");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_NOT_SUPPORTED:
ERROR("BUG: controller reported that it doesn't support default parameters");
LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
return ERROR_NAND_OPERATION_FAILED;
default:
ERROR("BUG: unknown controller initialization failure");
LOG_ERROR("BUG: unknown controller initialization failure");
return ERROR_NAND_OPERATION_FAILED;
}
}
@@ -452,12 +452,12 @@ int nand_probe(struct nand_device_s *device)
if (!device->device)
{
ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
manufacturer_id, device_id);
return ERROR_NAND_OPERATION_FAILED;
}
DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
/* initialize device parameters */
@@ -499,7 +499,7 @@ int nand_probe(struct nand_device_s *device)
}
else if (device->device->page_size == 256)
{
ERROR("NAND flashes with 256 byte pagesize are not supported");
LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
return ERROR_NAND_OPERATION_FAILED;
}
else
@@ -517,7 +517,7 @@ int nand_probe(struct nand_device_s *device)
device->address_cycles = 4;
else
{
ERROR("BUG: small page NAND device with more than 8 GiB encountered");
LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
device->address_cycles = 5;
}
}
@@ -530,7 +530,7 @@ int nand_probe(struct nand_device_s *device)
device->address_cycles = 5;
else
{
ERROR("BUG: small page NAND device with more than 32 GiB encountered");
LOG_ERROR("BUG: small page NAND device with more than 32 GiB encountered");
device->address_cycles = 6;
}
}
@@ -564,14 +564,14 @@ int nand_probe(struct nand_device_s *device)
switch (retval)
{
case ERROR_NAND_OPERATION_FAILED:
DEBUG("controller initialization failed");
LOG_DEBUG("controller initialization failed");
return ERROR_NAND_OPERATION_FAILED;
case ERROR_NAND_OPERATION_NOT_SUPPORTED:
ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
device->bus_width, device->address_cycles, device->page_size);
return ERROR_NAND_OPERATION_FAILED;
default:
ERROR("BUG: unknown controller initialization failure");
LOG_ERROR("BUG: unknown controller initialization failure");
return ERROR_NAND_OPERATION_FAILED;
}
}
@@ -651,19 +651,19 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block)
if (!device->controller->nand_ready(device, 1000))
{
ERROR("timeout waiting for NAND flash block erase to complete");
LOG_ERROR("timeout waiting for NAND flash block erase to complete");
return ERROR_NAND_OPERATION_TIMEOUT;
}
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
{
ERROR("couldn't read status");
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
if (status & 0x1)
{
ERROR("erase operation didn't pass, status: 0x%2.2x", status);
LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
return ERROR_NAND_OPERATION_FAILED;
}
}
@@ -680,7 +680,7 @@ int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 dat
if (address % device->page_size)
{
ERROR("reads need to be page aligned");
LOG_ERROR("reads need to be page aligned");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -717,7 +717,7 @@ int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 da
if (address % device->page_size)
{
ERROR("writes need to be page aligned");
LOG_ERROR("writes need to be page aligned");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -976,13 +976,13 @@ int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 da
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
{
ERROR("couldn't read status");
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
if (status & NAND_STATUS_FAIL)
{
ERROR("write operation didn't pass, status: 0x%2.2x", status);
LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
return ERROR_NAND_OPERATION_FAILED;
}


+ 1
- 1
src/flash/non_cfi.c View File

@@ -250,7 +250,7 @@ void cfi_fixup_non_cfi(flash_bank_t *bank, void *param)
cfi_info->pri_ext = pri_ext;
} else if ((cfi_info->pri_id == 0x1) || (cfi_info->pri_id == 0x3))
{
ERROR("BUG: non-CFI flashes using the Intel commandset are not yet supported");
LOG_ERROR("BUG: non-CFI flashes using the Intel commandset are not yet supported");
exit(-1);
}
}


+ 3
- 3
src/flash/s3c2410_nand.c View File

@@ -99,7 +99,7 @@ int s3c2410_write_data(struct nand_device_s *device, u16 data)
target_t *target = s3c24xx_info->target;

if (target->state != TARGET_HALTED) {
ERROR("target must be halted to use S3C24XX NAND flash controller");
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -113,7 +113,7 @@ int s3c2410_read_data(struct nand_device_s *device, void *data)
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
ERROR("target must be halted to use S3C24XX NAND flash controller");
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}

@@ -128,7 +128,7 @@ int s3c2410_nand_ready(struct nand_device_s *device, int timeout)
u8 status;

if (target->state != TARGET_HALTED) {
ERROR("target must be halted to use S3C24XX NAND flash controller");
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}


+ 4
- 4
src/flash/s3c2440_nand.c View File

@@ -104,7 +104,7 @@ int s3c2440_nand_ready(struct nand_device_s *device, int timeout)
u8 status;

if (target->state != TARGET_HALTED) {
ERROR("target must be halted to use S3C24XX NAND flash controller");
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -130,10 +130,10 @@ int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_siz
u32 nfdata = s3c24xx_info->data;
u32 tmp;

INFO("%s: reading data: %p, %p, %d\n", __func__, device, data, data_size);
LOG_INFO("%s: reading data: %p, %p, %d\n", __func__, device, data, data_size);

if (target->state != TARGET_HALTED) {
ERROR("target must be halted to use S3C24XX NAND flash controller");
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}

@@ -167,7 +167,7 @@ int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_si
u32 tmp;

if (target->state != TARGET_HALTED) {
ERROR("target must be halted to use S3C24XX NAND flash controller");
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}



+ 7
- 7
src/flash/s3c24xx_nand.c View File

@@ -47,7 +47,7 @@ s3c24xx_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t));
if (s3c24xx_info == NULL) {
ERROR("no memory for nand controller\n");
LOG_ERROR("no memory for nand controller\n");
return NULL;
}