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@@ -58,6 +58,7 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm |
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static int etb_set_instr(etb_t *etb, u32 new_instr) |
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{ |
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jtag_tap_t *tap; |
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tap = etb->tap; |
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if (tap==NULL) |
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return ERROR_FAIL; |
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@@ -73,10 +74,6 @@ static int etb_set_instr(etb_t *etb, u32 new_instr) |
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field.in_value = NULL; |
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jtag_add_ir_scan(1, &field, TAP_INVALID); |
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free(field.out_value); |
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@@ -87,7 +84,7 @@ static int etb_set_instr(etb_t *etb, u32 new_instr) |
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static int etb_scann(etb_t *etb, u32 new_scan_chain) |
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{ |
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if(etb->cur_scan_chain != new_scan_chain) |
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if (etb->cur_scan_chain != new_scan_chain) |
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{ |
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scan_field_t field; |
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@@ -98,10 +95,6 @@ static int etb_scann(etb_t *etb, u32 new_scan_chain) |
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field.in_value = NULL; |
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/* select INTEST instruction */ |
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etb_set_instr(etb, 0x2); |
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jtag_add_dr_scan(1, &field, TAP_INVALID); |
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@@ -159,6 +152,7 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb) |
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static int etb_get_reg(reg_t *reg) |
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{ |
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int retval; |
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if ((retval = etb_read_reg(reg)) != ERROR_OK) |
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{ |
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LOG_ERROR("BUG: error scheduling etm register read"); |
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@@ -188,25 +182,21 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames) |
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fields[0].out_value = NULL; |
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u8 tmp[4]; |
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fields[0].in_value = tmp; |
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fields[1].tap = etb->tap; |
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fields[1].num_bits = 7; |
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fields[1].out_value = malloc(1); |
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buf_set_u32(fields[1].out_value, 0, 7, 4); |
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fields[1].in_value = NULL; |
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fields[2].tap = etb->tap; |
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fields[2].num_bits = 1; |
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fields[2].out_value = malloc(1); |
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buf_set_u32(fields[2].out_value, 0, 1, 0); |
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fields[2].in_value = NULL; |
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jtag_add_dr_scan(3, fields, TAP_INVALID); |
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for (i = 0; i < num_frames; i++) |
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{ |
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/* ensure nR/W reamins set to read */ |
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@@ -246,35 +236,20 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) |
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fields[0].tap = etb_reg->etb->tap; |
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fields[0].num_bits = 32; |
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fields[0].out_value = reg->value; |
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fields[0].in_value = NULL; |
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fields[1].tap = etb_reg->etb->tap; |
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fields[1].num_bits = 7; |
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fields[1].out_value = malloc(1); |
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buf_set_u32(fields[1].out_value, 0, 7, reg_addr); |
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fields[1].in_value = NULL; |
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fields[2].tap = etb_reg->etb->tap; |
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fields[2].num_bits = 1; |
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fields[2].out_value = malloc(1); |
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buf_set_u32(fields[2].out_value, 0, 1, 0); |
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fields[2].in_value = NULL; |
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jtag_add_dr_scan(3, fields, TAP_INVALID); |
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/* read the identification register in the second run, to make sure we |
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@@ -301,6 +276,7 @@ int etb_read_reg(reg_t *reg) |
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int etb_set_reg(reg_t *reg, u32 value) |
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{ |
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int retval; |
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if ((retval = etb_write_reg(reg, value)) != ERROR_OK) |
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{ |
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LOG_ERROR("BUG: error scheduling etm register write"); |
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@@ -317,6 +293,7 @@ int etb_set_reg(reg_t *reg, u32 value) |
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int etb_set_reg_w_exec(reg_t *reg, u8 *buf) |
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{ |
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int retval; |
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etb_set_reg(reg, buf_get_u32(buf, 0, reg->size)); |
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if ((retval = jtag_execute_queue()) != ERROR_OK) |
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@@ -343,24 +320,14 @@ int etb_write_reg(reg_t *reg, u32 value) |
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fields[0].num_bits = 32; |
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fields[0].out_value = malloc(4); |
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buf_set_u32(fields[0].out_value, 0, 32, value); |
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fields[0].in_value = NULL; |
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fields[1].tap = etb_reg->etb->tap; |
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fields[1].num_bits = 7; |
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fields[1].out_value = malloc(1); |
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buf_set_u32(fields[1].out_value, 0, 7, reg_addr); |
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fields[1].in_value = NULL; |
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fields[2].tap = etb_reg->etb->tap; |
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fields[2].num_bits = 1; |
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fields[2].out_value = malloc(1); |
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@@ -368,12 +335,6 @@ int etb_write_reg(reg_t *reg, u32 value) |
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fields[2].in_value = NULL; |
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jtag_add_dr_scan(3, fields, TAP_INVALID); |
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free(fields[0].out_value); |
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free(fields[1].out_value); |
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free(fields[2].out_value); |
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@@ -424,12 +385,12 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm |
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} |
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tap = jtag_TapByString( args[1] ); |
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if( tap == NULL ){ |
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if (tap == NULL) |
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{ |
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command_print(cmd_ctx, "Tap: %s does not exist", args[1] ); |
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return ERROR_FAIL; |
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} |
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if (arm7_9->etm_ctx) |
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{ |
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etb_t *etb = malloc(sizeof(etb_t)); |
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