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@@ -749,7 +749,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) |
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LOG_WARNING("breakpoint already set"); |
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return ERROR_OK; |
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} |
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if (cortex_m3->auto_bp_type) |
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{ |
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breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; |
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@@ -831,10 +831,16 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) |
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/* get pointers to arch-specific information */ |
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armv7m_common_t *armv7m = target->arch_info; |
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info; |
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if (cortex_m3->auto_bp_type) |
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{ |
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breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; |
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if (breakpoint->length != 2) { |
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// XXX Hack: Replace all breakpoints with length != 2 with |
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// a hardware breakpoint. |
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breakpoint->type = BKPT_HARD; |
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breakpoint->length = 2; |
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} |
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} |
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if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000)) |
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@@ -1105,6 +1111,14 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty |
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info; |
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info; |
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// If the LR register is being modified, make sure it will put us |
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// in "thumb" mode, or an INVSTATE exception will occur. This is a |
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// hack to deal with the fact that gdb will sometimes "forge" |
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// return addresses, and doesn't set the LSB correctly (i.e., when |
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// printing expressions containing function calls, it sets LR=0.) |
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if (num==14) |
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value |= 0x01; |
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if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) |
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{ |
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retval = ahbap_write_coreregister_u32(swjdp, value, num); |
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@@ -1449,3 +1463,4 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx) |
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return retval; |
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} |
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