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/*************************************************************************** |
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* Copyright (C) 2011 by Marc Willam, Holger Wech * |
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* m.willam@gmx.eu * |
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* Copyright (C) 2011 Ronny Strutz * |
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* * |
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* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License as published by * |
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* the Free Software Foundation; either version 2 of the License, or * |
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* (at your option) any later version. * |
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* * |
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* This program is distributed in the hope that it will be useful, * |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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* GNU General Public License for more details. * |
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* * |
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* You should have received a copy of the GNU General Public License * |
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* along with this program; if not, write to the * |
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* Free Software Foundation, Inc., * |
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * |
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***************************************************************************/ |
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#ifdef HAVE_CONFIG_H |
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#include "config.h" |
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#endif |
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#include "imp.h" |
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#include <helper/binarybuffer.h> |
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#include <target/algorithm.h> |
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#include <target/armv7m.h> |
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#define FLASH_DQ6 0x00000040 /* Data toggle flag bit (TOGG) position */ |
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#define FLASH_DQ5 0x00000020 /* Time limit exceeding flag bit (TLOV) position */ |
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enum fm3_variant |
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{ |
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mb9bfxx1, |
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mb9bfxx2, |
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mb9bfxx3, |
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mb9bfxx4, |
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mb9bfxx5, |
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mb9bfxx6 |
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}; |
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struct fm3_flash_bank |
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{ |
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struct working_area *write_algorithm; |
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enum fm3_variant variant; |
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int probed; |
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}; |
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FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command) |
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{ |
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struct fm3_flash_bank *fm3_info; |
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if (CMD_ARGC < 6) |
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{ |
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LOG_WARNING("incomplete flash_bank fm3 configuration"); |
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return ERROR_FLASH_BANK_INVALID; |
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} |
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LOG_INFO("******HWE* FLASH CMD Parameter %s", CMD_ARGV[5]); |
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fm3_info = malloc(sizeof(struct fm3_flash_bank)); |
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bank->driver_priv = fm3_info; |
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if (strcmp(CMD_ARGV[5], "mb9bfxx1.cpu") == 0) |
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{ |
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fm3_info->variant = mb9bfxx1; |
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} |
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else if (strcmp(CMD_ARGV[5], "mb9bfxx2.cpu") == 0) |
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{ |
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fm3_info->variant = mb9bfxx2; |
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} |
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else if (strcmp(CMD_ARGV[5], "mb9bfxx3.cpu") == 0) |
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{ |
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fm3_info->variant = mb9bfxx3; |
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} |
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else if (strcmp(CMD_ARGV[5], "mb9bfxx4.cpu") == 0) |
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{ |
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fm3_info->variant = mb9bfxx4; |
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} |
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else if (strcmp(CMD_ARGV[5], "mb9bfxx5.cpu") == 0) |
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{ |
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fm3_info->variant = mb9bfxx5; |
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} |
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else if (strcmp(CMD_ARGV[5], "mb9bfxx6.cpu") == 0) |
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{ |
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fm3_info->variant = mb9bfxx6; |
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LOG_INFO("******HWE* fm3 Variant set to: mb9bfxx6"); |
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} |
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else |
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{ |
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LOG_ERROR("unknown fm3 variant: %s", CMD_ARGV[5]); |
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free(fm3_info); |
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return ERROR_FLASH_BANK_INVALID; |
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} |
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fm3_info->write_algorithm = NULL; |
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fm3_info->probed = 0; |
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return ERROR_OK; |
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} |
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static int fm3_busy_wait(struct target *target, uint32_t offset, int timeout_ms) |
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{ |
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int retval = ERROR_OK; |
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uint16_t state1, state2; |
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int ms = 0; |
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while(1) { |
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target_read_u16(target, offset, &state1); /* dummy-read - see flash manual */ |
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target_read_u16(target, offset, &state1); |
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target_read_u16(target, offset, &state2); |
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if ( (state1 & FLASH_DQ6) == (state2 & FLASH_DQ6) ) { |
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break; |
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} |
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else if (state1 & FLASH_DQ5) { |
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target_read_u16(target, offset, &state1); |
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target_read_u16(target, offset, &state2); |
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if ( (state1 & FLASH_DQ6) != (state2 & FLASH_DQ6) ) |
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retval = ERROR_FLASH_OPERATION_FAILED; |
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break; |
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} |
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usleep(1000); |
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++ms; |
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if (ms > timeout_ms) { |
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LOG_ERROR("toggle bit reading timed out!"); |
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retval = ERROR_FLASH_OPERATION_FAILED; |
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break; |
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} |
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} |
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if (retval == ERROR_OK) |
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LOG_DEBUG("fm3_busy_wait(%x) needs about %d ms", offset, ms); |
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return retval; |
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} |
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static int fm3_erase(struct flash_bank *bank, int first, int last) |
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{ |
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struct target *target = bank->target; |
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int retval = ERROR_OK; |
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uint32_t u32DummyRead; |
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int sector, odd; |
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if (target->state != TARGET_HALTED) { |
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LOG_ERROR("Target not halted"); |
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return ERROR_TARGET_NOT_HALTED; |
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} |
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LOG_INFO("Fujitsu MB9Bxxx: Sector Erase ... (%d to %d)", first, last); |
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target_write_u32(target, 0x40000000, 0x0001); /* FASZR = 0x01, Enables CPU Programming Mode */ |
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target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */ |
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for (sector = first ; sector <= last ; sector++) { |
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uint32_t offset = bank->sectors[sector].offset; |
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for (odd = 0; odd < 2 ; odd++) { |
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if (odd) |
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offset += 4; |
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target_write_u16(target, 0x1550, 0x00AA); |
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target_write_u16(target, 0x0AA8, 0x0055); |
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target_write_u16(target, 0x1550, 0x0080); |
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target_write_u16(target, 0x1550, 0x00AA); |
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target_write_u16(target, 0x0AA8, 0x0055); |
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target_write_u16(target, offset, 0x0030); |
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retval = fm3_busy_wait(target, offset, 500); |
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if (retval != ERROR_OK) |
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break; |
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} |
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bank->sectors[sector].is_erased = 1; |
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} |
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target_write_u32(target, 0x40000000, 0x0002); |
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target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */ |
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return retval; |
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} |
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static int fm3_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count) |
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{ |
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struct fm3_flash_bank *fm3_info = bank->driver_priv; |
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struct target *target = bank->target; |
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uint32_t buffer_size = 8192; |
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struct working_area *source; |
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uint32_t address = bank->base + offset; |
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struct reg_param reg_params[4]; |
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struct armv7m_algorithm armv7m_info; |
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int retval = ERROR_OK; |
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/* RAMCODE used for fm3 Flash programming: */ |
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/* R0 keeps source start address (u32Source) */ |
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/* R1 keeps target start address (u32Target) */ |
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/* R2 keeps number of halfwords to write (u32Count) */ |
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/* R3 returns result value (u32FlashResult) */ |
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const uint8_t fm3_flash_write_code[] = { |
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/* fm3_FLASH_IF->FASZ &= 0xFFFD; */ |
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0x00, 0xBF, /* NOP */ |
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0x5F, 0xF0, 0x80, 0x43, /* MOVS.W R3, #(fm3_FLASH_IF->FASZ) */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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0x4F, 0xF6, 0xFD, 0x74, /* MOVW R4, #0xFFFD */ |
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0x23, 0x40, /* ANDS R3, R3, R4 */ |
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0x5F, 0xF0, 0x80, 0x44, /* MOVS.W R4, #(fm3_FLASH_IF->FASZ) */ |
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0x23, 0x60, /* STR R3, [R4] */ |
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/* fm3_FLASH_IF->FASZ |= 1; */ |
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0x5F, 0xF0, 0x80, 0x43, /* MOVS.W R3, #(fm3_FLASH_IF->FASZ) */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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0x53, 0xF0, 0x01, 0x03, /* ORRS.W R3, R3, #1 */ |
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0x5F, 0xF0, 0x80, 0x44, /* MOVS.W R4, #(fm3_FLASH_IF->FASZ) */ |
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0x23, 0x60, /* STR R3, [R4] */ |
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/* u32DummyRead = fm3_FLASH_IF->FASZ; */ |
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0x2B, 0x4B, /* LDR.N R3, ??u32DummyRead */ |
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0x5F, 0xF0, 0x80, 0x44, /* MOVS.W R4, #(fm3_FLASH_IF->FASZ) */ |
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0x24, 0x68, /* LDR R4, [R4] */ |
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0x1C, 0x60, /* STR R4, [R3] */ |
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/* u32FlashResult = FLASH_WRITE_NO_RESULT */ |
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0x2A, 0x4B, /* LDR.N R3, ??u32FlashResult */ |
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0x00, 0x24, /* MOVS R4, #0 */ |
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0x1C, 0x60, /* STR R4, [R3] */ |
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/* while ((u32Count > 0 ) && (u32FlashResult */ |
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/* == FLASH_WRITE_NO_RESULT)) */ |
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0x01, 0x2A, /* L0: CMP R2, #1 */ |
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0x32, 0xDB, /* BLT.N L1 */ |
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0x27, 0x4B, /* LDR.N R3, ??u32FlashResult */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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0x00, 0x2B, /* CMP R3, #0 */ |
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0x2E, 0xD1, /* BNE.N L1 */ |
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/* *(FLASH_SEQ_1550) = FLASH_WRITE_1; */ |
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0x41, 0xF2, 0x50, 0x53, /* MOVW R3, #0x1550 */ |
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0xAA, 0x24, /* MOVS R4. #0xAA */ |
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0x1C, 0x80, /* STRH R4, [R3] */ |
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/* *(FLASH_SEQ_0AA8) = FLASH_WRITE_2; */ |
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0x40, 0xF6, 0xA8, 0x23, /* MOVW R3, #0x0AA8 */ |
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0x55, 0x24, /* MOVS R4. #0x55 */ |
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0x1C, 0x80, /* STRH R4, [R3] */ |
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/* *(FLASH_SEQ_1550) = FLASH_WRITE_3; */ |
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0x41, 0xF2, 0x50, 0x53, /* MOVW R3, #0x1550 */ |
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0xA0, 0x24, /* MOVS R4. #0xA0 */ |
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0x1C, 0x80, /* STRH R4, [R3] */ |
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/* *(volatile uint16_t*)u32Target */ |
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/* = *(volatile uint16_t*)u32Source; */ |
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0x03, 0x88, /* LDRH R3, [R0] */ |
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0x0B, 0x80, /* STRH R3, [R1] */ |
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/* while (u32FlashResult == FLASH_WRITE_NO_RESTULT) */ |
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0x1E, 0x4B, /* L2: LDR.N R3, ??u32FlashResult */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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0x00, 0x2B, /* CMP R3, #0 */ |
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0x11, 0xD1, /* BNE.N L3 */ |
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/* if ((*(volatile uint16_t*)u32Target & FLASH_DQ5) */ |
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/* == FLASH_DQ5) */ |
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0x0B, 0x88, /* LDRH R3, [R1] */ |
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0x9B, 0x06, /* LSLS R3, R3, #0x1A */ |
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0x02, 0xD5, /* BPL.N L4 */ |
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/* u32FlashResult = FLASH_WRITE_TIMEOUT */ |
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0x1B, 0x4B, /* LDR.N R3, ??u32FlashResult */ |
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0x02, 0x24, /* MOVS R4, #2 */ |
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0x1C, 0x60, /* STR R4, [R3] */ |
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/* if ((*(volatile uint16_t *)u32Target & FLASH_DQ7) */ |
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/* == (*(volatile uint16_t*)u32Source & FLASH_DQ7)) */ |
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0x0B, 0x88, /* L4: LDRH R3, [R1] */ |
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0x13, 0xF0, 0x80, 0x03, /* ANDS.W R3, R3, #0x80 */ |
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0x04, 0x88, /* LDRH R4, [R0] */ |
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0x14, 0xF0, 0x80, 0x04, /* ANDS.W R4, R4, #0x80 */ |
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0xA3, 0x42, /* CMP R3, R4 */ |
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0xED, 0xD1, /* BNE.N L2 */ |
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/* u32FlashResult = FLASH_WRITE_OKAY */ |
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0x15, 0x4B, /* LDR.N R3, ??u32FlashResult */ |
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0x01, 0x24, /* MOVS R4, #1 */ |
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0x1C, 0x60, /* STR R4, [R3] */ |
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0xE9, 0xE7, /* B.N L2 */ |
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/* if (u32FlashResult != FLASH_WRITE_TIMEOUT) */ |
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0x13, 0x4B, /* LDR.N R3, ??u32FlashResult */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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0x02, 0x2B, /* CMP R3, #2 */ |
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0x02, 0xD0, /* BEQ.N L5 */ |
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/* u32FlashResult = FLASH_WRITE_NO_RESULT */ |
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0x11, 0x4B, /* LDR.N R3, ??u32FlashResult */ |
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0x00, 0x24, /* MOVS R4, #0 */ |
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0x1C, 0x60, /* STR R4, [R3] */ |
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/* u32Count--; */ |
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0x52, 0x1E, /* L5: SUBS R2, R2, #1 */ |
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/* u32Source += 2; */ |
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0x80, 0x1C, /* ADDS R0, R0, #2 */ |
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/* u32Target += 2; */ |
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0x89, 0x1C, /* ADDS R1, R1, #2 */ |
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0xCA, 0xE7, /* B.N L0 */ |
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/* fm3_FLASH_IF->FASZ &= 0xFFFE; */ |
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0x5F, 0xF0, 0x80, 0x43, /* L1: MOVS.W R3, #(fm3_FLASH_IF->FASZ) */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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0x4F, 0xF6, 0xFE, 0x74, /* MOVW R4, #0xFFFE */ |
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0x23, 0x40, /* ANDS R3, R3, R4 */ |
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0x5F, 0xF0, 0x80, 0x44, /* MOVS.W R4, #(fm3_FLASH_IF->FASZ) */ |
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0x23, 0x60, /* STR R3, [R4] */ |
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/* fm3_FLASH_IF->FASZ |= 2; */ |
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0x5F, 0xF0, 0x80, 0x43, /* MOVS.W R3, #(fm3_FLASH_IF->FASZ) */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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0x53, 0xF0, 0x02, 0x03, /* ORRS.W R3, R3, #2 */ |
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0x5F, 0xF0, 0x80, 0x44, /* MOVS.W R4, #(fm3_FLASH_IF->FASZ) */ |
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0x23, 0x60, /* STR R4, [R3] */ |
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/* u32DummyRead = fm3_FLASH_IF->FASZ; */ |
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0x04, 0x4B, /* LDR.N R3, ??u32DummyRead */ |
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0x5F, 0xF0, 0x80, 0x44, /* MOVS.W R4, #(fm3_FLASH_IF->FASZ) */ |
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0x24, 0x68, /* LDR R4, [R4] */ |
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0x1C, 0x60, /* STR R4, [R3] */ |
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/* copy u32FlashResult to R3 for return value */ |
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0xDF, 0xF8, 0x0C, 0x30, /* LDR.W R3, ??u32FlashResult */ |
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0x1B, 0x68, /* LDR R3, [R3] */ |
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/* Breakpoint here */ |
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0x00, 0xBE, /* Breakpoint #0 */ |
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0x00, 0x00, /* alignment padding bytes */ |
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0x00, 0x80, 0xFF, 0x1F, /* u32DummyRead address in RAM (0x1FFF8000) */ |
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0x04, 0x80, 0xFF, 0x1F /* u32FlashResult address in RAM (0x1FFF8004) */ |
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}; |
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LOG_INFO("Fujitsu MB9B500: FLASH Write ..."); |
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/* disable HW watchdog */ |
|
|
|
target_write_u32(target, 0x40011C00, 0x1ACCE551); |
|
|
|
target_write_u32(target, 0x40011C00, 0xE5331AAE); |
|
|
|
target_write_u32(target, 0x40011008, 0x00000000); |
|
|
|
|
|
|
|
count = count / 2; /* number bytes -> number halfwords */ |
|
|
|
|
|
|
|
/* check code alignment */ |
|
|
|
if (offset & 0x1) |
|
|
|
{ |
|
|
|
LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset); |
|
|
|
return ERROR_FLASH_DST_BREAKS_ALIGNMENT; |
|
|
|
} |
|
|
|
|
|
|
|
/* allocate working area with flash programming code */ |
|
|
|
if (target_alloc_working_area(target, sizeof(fm3_flash_write_code), |
|
|
|
&fm3_info->write_algorithm) != ERROR_OK) |
|
|
|
{ |
|
|
|
LOG_WARNING("no working area available, can't do block memory writes"); |
|
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; |
|
|
|
} |
|
|
|
|
|
|
|
retval = target_write_buffer(target, fm3_info->write_algorithm->address, |
|
|
|
sizeof(fm3_flash_write_code), fm3_flash_write_code); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
|
|
|
|
/* memory buffer */ |
|
|
|
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) |
|
|
|
{ |
|
|
|
buffer_size /= 2; |
|
|
|
if (buffer_size <= 256) |
|
|
|
{ |
|
|
|
/* free working area, if write algorithm already allocated */ |
|
|
|
if (fm3_info->write_algorithm) |
|
|
|
{ |
|
|
|
target_free_working_area(target, fm3_info->write_algorithm); |
|
|
|
} |
|
|
|
|
|
|
|
LOG_WARNING("no large enough working area available, can't do block memory writes"); |
|
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; |
|
|
|
armv7m_info.core_mode = ARMV7M_MODE_ANY; |
|
|
|
|
|
|
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT); // source start address |
|
|
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); // target start address |
|
|
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); // number of halfwords to program |
|
|
|
init_reg_param(®_params[3], "r3", 32, PARAM_IN); // result |
|
|
|
|
|
|
|
/* write code buffer and use Flash programming code within fm3 */ |
|
|
|
/* Set breakpoint to 0 with time-out of 1000 ms */ |
|
|
|
while (count > 0) |
|
|
|
{ |
|
|
|
uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count; |
|
|
|
|
|
|
|
/* for some reason the first 8 byte of code are corrupt when target_run_algorithm() returns */ |
|
|
|
/* need some more investigation on this */ |
|
|
|
retval = target_write_buffer(target, |
|
|
|
fm3_info->write_algorithm->address, 8, fm3_flash_write_code); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
|
|
|
|
|
|
|
|
retval = target_write_buffer(target, |
|
|
|
source->address, thisrun_count * 2, buffer); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
break; |
|
|
|
|
|
|
|
buf_set_u32(reg_params[0].value, 0, 32, source->address); |
|
|
|
buf_set_u32(reg_params[1].value, 0, 32, address); |
|
|
|
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count); |
|
|
|
|
|
|
|
|
|
|
|
retval = target_run_algorithm(target, 0, NULL, 4, reg_params, |
|
|
|
fm3_info->write_algorithm->address, 0, 1000, &armv7m_info); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
{ |
|
|
|
LOG_ERROR("error executing fm3 Flash programming algorithm"); |
|
|
|
retval = ERROR_FLASH_OPERATION_FAILED; |
|
|
|
break; |
|
|
|
} |
|
|
|
|
|
|
|
#if 0 |
|
|
|
/* debug the corrupted 8 bytes */ |
|
|
|
unsigned char buf[256]; |
|
|
|
retval = target_read_buffer(target, fm3_info->write_algorithm->address, 256, buf); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
printf("cannot read buffer\n"); |
|
|
|
unsigned int i; |
|
|
|
for ( i = 0; i < sizeof(fm3_flash_write_code); i++) |
|
|
|
if (buf[i] != fm3_flash_write_code[i]) |
|
|
|
printf("broken: %d %02x != %02x\n", i, buf[i], fm3_flash_write_code[i]); |
|
|
|
#endif |
|
|
|
|
|
|
|
if (buf_get_u32(reg_params[3].value, 0, 32) != ERROR_OK) |
|
|
|
{ |
|
|
|
LOG_ERROR("Fujitsu MB9B500: FLASH programming ERROR (Timeout) -> Reg R3: %x", |
|
|
|
buf_get_u32(reg_params[3].value, 0, 32)); |
|
|
|
retval = ERROR_FLASH_OPERATION_FAILED; |
|
|
|
break; |
|
|
|
} |
|
|
|
|
|
|
|
buffer += thisrun_count * 2; |
|
|
|
address += thisrun_count * 2; |
|
|
|
count -= thisrun_count; |
|
|
|
} |
|
|
|
|
|
|
|
target_free_working_area(target, source); |
|
|
|
target_free_working_area(target, fm3_info->write_algorithm); |
|
|
|
|
|
|
|
destroy_reg_param(®_params[0]); |
|
|
|
destroy_reg_param(®_params[1]); |
|
|
|
destroy_reg_param(®_params[2]); |
|
|
|
destroy_reg_param(®_params[3]); |
|
|
|
|
|
|
|
return retval; |
|
|
|
} |
|
|
|
|
|
|
|
static int fm3_probe(struct flash_bank *bank) |
|
|
|
{ |
|
|
|
struct fm3_flash_bank *fm3_info = bank->driver_priv; |
|
|
|
uint16_t num_pages; |
|
|
|
|
|
|
|
if (bank->target->state != TARGET_HALTED) |
|
|
|
{ |
|
|
|
LOG_ERROR("Target not halted"); |
|
|
|
return ERROR_TARGET_NOT_HALTED; |
|
|
|
} |
|
|
|
|
|
|
|
num_pages = 6; /* max number of Flash pages for malloc */ |
|
|
|
fm3_info->probed = 0; |
|
|
|
|
|
|
|
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages); |
|
|
|
bank->base = 0x00000000; |
|
|
|
num_pages = 2; /* start with smallest Flash pages number */ |
|
|
|
bank->size = 32 * 1024; /* bytes */ |
|
|
|
|
|
|
|
bank->sectors[0].offset = 0; |
|
|
|
bank->sectors[0].size = 16 * 1024; |
|
|
|
bank->sectors[0].is_erased = -1; |
|
|
|
bank->sectors[0].is_protected = -1; |
|
|
|
|
|
|
|
bank->sectors[1].offset = 0x4000; |
|
|
|
bank->sectors[1].size = 16 * 1024; |
|
|
|
bank->sectors[1].is_erased = -1; |
|
|
|
bank->sectors[1].is_protected = -1; |
|
|
|
|
|
|
|
if (fm3_info->variant == mb9bfxx1) |
|
|
|
{ |
|
|
|
num_pages = 3; |
|
|
|
bank->size = 64 * 1024; /* bytes */ |
|
|
|
bank->num_sectors = num_pages; |
|
|
|
|
|
|
|
bank->sectors[2].offset = 0x8000; |
|
|
|
bank->sectors[2].size = 32 * 1024; |
|
|
|
bank->sectors[2].is_erased = -1; |
|
|
|
bank->sectors[2].is_protected = -1; |
|
|
|
} |
|
|
|
|
|
|
|
if ( (fm3_info->variant == mb9bfxx2) |
|
|
|
|| (fm3_info->variant == mb9bfxx4) |
|
|
|
|| (fm3_info->variant == mb9bfxx5) |
|
|
|
|| (fm3_info->variant == mb9bfxx6)) |
|
|
|
{ |
|
|
|
num_pages = 3; |
|
|
|
bank->size = 128 * 1024; // bytes |
|
|
|
bank->num_sectors = num_pages; |
|
|
|
|
|
|
|
bank->sectors[2].offset = 0x8000; |
|
|
|
bank->sectors[2].size = 96 * 1024; |
|
|
|
bank->sectors[2].is_erased = -1; |
|
|
|
bank->sectors[2].is_protected = -1; |
|
|
|
} |
|
|
|
|
|
|
|
if ( (fm3_info->variant == mb9bfxx4) |
|
|
|
|| (fm3_info->variant == mb9bfxx5) |
|
|
|
|| (fm3_info->variant == mb9bfxx6)) |
|
|
|
{ |
|
|
|
num_pages = 4; |
|
|
|
bank->size = 256 * 1024; // bytes |
|
|
|
bank->num_sectors = num_pages; |
|
|
|
|
|
|
|
bank->sectors[3].offset = 0x20000; |
|
|
|
bank->sectors[3].size = 128 * 1024; |
|
|
|
bank->sectors[3].is_erased = -1; |
|
|
|
bank->sectors[3].is_protected = -1; |
|
|
|
} |
|
|
|
|
|
|
|
if ( (fm3_info->variant == mb9bfxx5) |
|
|
|
|| (fm3_info->variant == mb9bfxx6)) |
|
|
|
{ |
|
|
|
num_pages = 5; |
|
|
|
bank->size = 384 * 1024; // bytes |
|
|
|
bank->num_sectors = num_pages; |
|
|
|
|
|
|
|
bank->sectors[4].offset = 0x40000; |
|
|
|
bank->sectors[4].size = 128 * 1024; |
|
|
|
bank->sectors[4].is_erased = -1; |
|
|
|
bank->sectors[4].is_protected = -1; |
|
|
|
} |
|
|
|
|
|
|
|
if (fm3_info->variant == mb9bfxx6) |
|
|
|
{ |
|
|
|
num_pages = 6; |
|
|
|
bank->size = 512 * 1024; // bytes |
|
|
|
bank->num_sectors = num_pages; |
|
|
|
|
|
|
|
bank->sectors[5].offset = 0x60000; |
|
|
|
bank->sectors[5].size = 128 * 1024; |
|
|
|
bank->sectors[5].is_erased = -1; |
|
|
|
bank->sectors[5].is_protected = -1; |
|
|
|
} |
|
|
|
|
|
|
|
fm3_info->probed = 1; |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int fm3_auto_probe(struct flash_bank *bank) |
|
|
|
{ |
|
|
|
struct fm3_flash_bank *fm3_info = bank->driver_priv; |
|
|
|
if (fm3_info->probed) |
|
|
|
return ERROR_OK; |
|
|
|
return fm3_probe(bank); |
|
|
|
} |
|
|
|
|
|
|
|
static int fm3_info(struct flash_bank *bank, char *buf, int buf_size) |
|
|
|
{ |
|
|
|
snprintf(buf, buf_size, "Fujitsu fm3 Device does not support Chip-ID (Type unknown)"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int fm3_chip_erase(struct flash_bank *bank) |
|
|
|
{ |
|
|
|
struct target *target = bank->target; |
|
|
|
int retval = ERROR_OK; |
|
|
|
uint32_t u32DummyRead; |
|
|
|
|
|
|
|
if (target->state != TARGET_HALTED) |
|
|
|
{ |
|
|
|
LOG_ERROR("Target not halted"); |
|
|
|
return ERROR_TARGET_NOT_HALTED; |
|
|
|
} |
|
|
|
|
|
|
|
LOG_INFO("Fujitsu MB9Bxxx: Chip Erase ... (may take several seconds)"); |
|
|
|
|
|
|
|
/* Implement Flash chip erase (mass erase) completely on host */ |
|
|
|
target_write_u32(target, 0x40000000, 0x0001); /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */ |
|
|
|
target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */ |
|
|
|
|
|
|
|
target_write_u16(target, 0x00001550, 0x00AA); /* Flash unlock sequence */ |
|
|
|
target_write_u16(target, 0x00000AA8, 0x0055); |
|
|
|
target_write_u16(target, 0x00001550, 0x0080); |
|
|
|
target_write_u16(target, 0x00001550, 0x00AA); |
|
|
|
target_write_u16(target, 0x00000AA8, 0x0055); |
|
|
|
target_write_u16(target, 0x00001550, 0x0010); /* Chip Erase command */ |
|
|
|
|
|
|
|
retval = fm3_busy_wait(target, 0xAA8, 20000); |
|
|
|
|
|
|
|
target_write_u32(target, 0x40000000, 0x0002); |
|
|
|
target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */ |
|
|
|
|
|
|
|
return retval; |
|
|
|
} |
|
|
|
|
|
|
|
COMMAND_HANDLER(fm3_handle_chip_erase_command) |
|
|
|
{ |
|
|
|
int i; |
|
|
|
|
|
|
|
if (CMD_ARGC < 1) |
|
|
|
{ |
|
|
|
command_print(CMD_CTX, "fm3 chip_erase <bank>"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
struct flash_bank *bank; |
|
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); |
|
|
|
if (ERROR_OK != retval) |
|
|
|
return retval; |
|
|
|
|
|
|
|
if (fm3_chip_erase(bank) == ERROR_OK) |
|
|
|
{ |
|
|
|
/* set all sectors as erased */ |
|
|
|
for (i = 0; i < bank->num_sectors; i++) |
|
|
|
bank->sectors[i].is_erased = 1; |
|
|
|
|
|
|
|
command_print(CMD_CTX, "fm3 chip erase complete"); |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
command_print(CMD_CTX, "fm3 chip erase failed"); |
|
|
|
} |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static const struct command_registration fm3_exec_command_handlers[] = { |
|
|
|
{ |
|
|
|
.name = "chip_erase", |
|
|
|
.handler = fm3_handle_chip_erase_command, |
|
|
|
.mode = COMMAND_EXEC, |
|
|
|
.usage = "bank_id", |
|
|
|
.help = "Erase entire Flash device.", |
|
|
|
}, |
|
|
|
COMMAND_REGISTRATION_DONE |
|
|
|
}; |
|
|
|
|
|
|
|
static const struct command_registration fm3_command_handlers[] = { |
|
|
|
{ |
|
|
|
.name = "fm3", |
|
|
|
.mode = COMMAND_ANY, |
|
|
|
.help = "fm3 Flash command group", |
|
|
|
.chain = fm3_exec_command_handlers, |
|
|
|
}, |
|
|
|
COMMAND_REGISTRATION_DONE |
|
|
|
}; |
|
|
|
|
|
|
|
struct flash_driver fm3_flash = { |
|
|
|
.name = "fm3", |
|
|
|
.commands = fm3_command_handlers, |
|
|
|
.flash_bank_command = fm3_flash_bank_command, |
|
|
|
.erase = fm3_erase, |
|
|
|
.write = fm3_write_block, |
|
|
|
.probe = fm3_probe, |
|
|
|
.auto_probe = fm3_auto_probe, |
|
|
|
.erase_check = default_flash_mem_blank_check, |
|
|
|
.info = fm3_info, |
|
|
|
}; |