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added target configs for the lpc17xx devices

lpc1751, lpc1752, lpc1754, lpc1756, lpc1758, lpc1759
lpc1763, lpc1764, lpc1765, lpc1766, lpc1767, lpc1768, lpc1769

Change-Id: I740b66930cd379c9390f3c1031cdbada747a6ce4
Signed-off-by: Vandra Akos <axos88@gmail.com>
Reviewed-on: http://openocd.zylin.com/676
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
tags/v0.6.0-rc1
Vandra Akos 12 years ago
committed by Freddie Chopin
parent
commit
ee8df96b2b
12 changed files with 248 additions and 0 deletions
  1. +21
    -0
      tcl/target/lpc1751.cfg
  2. +21
    -0
      tcl/target/lpc1752.cfg
  3. +21
    -0
      tcl/target/lpc1754.cfg
  4. +21
    -0
      tcl/target/lpc1756.cfg
  5. +21
    -0
      tcl/target/lpc1758.cfg
  6. +21
    -0
      tcl/target/lpc1759.cfg
  7. +21
    -0
      tcl/target/lpc1763.cfg
  8. +21
    -0
      tcl/target/lpc1764.cfg
  9. +21
    -0
      tcl/target/lpc1765.cfg
  10. +21
    -0
      tcl/target/lpc1766.cfg
  11. +21
    -0
      tcl/target/lpc1767.cfg
  12. +17
    -0
      tcl/target/lpc1769.cfg

+ 21
- 0
tcl/target/lpc1751.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM,
set CHIPNAME lpc1751
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x2000
set CPUROMSIZE 0x8000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1752.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB Local On-Chip SRAM,
set CHIPNAME lpc1752
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x4000
set CPUROMSIZE 0x10000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1754.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1754
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x4000
set CPUROMSIZE 0x20000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1756.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1756
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1758.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1758
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1759.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1759
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1763.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1763
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1764.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1764
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x4000
set CPUROMSIZE 0x20000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1765.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM,
set CHIPNAME lpc1765
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1766.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
set CHIPNAME lpc1766
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x40000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 21
- 0
tcl/target/lpc1767.cfg View File

@@ -0,0 +1,21 @@
# !!!!!!!!!!!!
# ! UNTESTED !
# !!!!!!!!!!!!

# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1767
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

+ 17
- 0
tcl/target/lpc1769.cfg View File

@@ -0,0 +1,17 @@
# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1769
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];

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