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@@ -2019,7 +2019,7 @@ int cortex_m_examine(struct target *target) |
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/* test for floating point feature on Cortex-M4 */ |
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if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) { |
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LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i); |
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armv7m->fp_feature = FPv4_SP; |
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armv7m->fp_feature = FPV4_SP; |
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} |
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} else if (i == 7 || i == 33 || i == 35 || i == 55) { |
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target_read_u32(target, MVFR0, &mvfr0); |
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@@ -2028,10 +2028,10 @@ int cortex_m_examine(struct target *target) |
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/* test for floating point features on Cortex-M7 */ |
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if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) { |
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LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i); |
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armv7m->fp_feature = FPv5_SP; |
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armv7m->fp_feature = FPV5_SP; |
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} else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) { |
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LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i); |
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armv7m->fp_feature = FPv5_DP; |
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armv7m->fp_feature = FPV5_DP; |
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} |
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} else if (i == 0) { |
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/* Cortex-M0 does not support unaligned memory access */ |
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