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@@ -731,7 +731,6 @@ int cortex_m3_assert_reset(target_t *target) |
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{ |
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if (retval == ERROR_JTAG_RESET_CANT_SRST) |
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{ |
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WARNING("can't assert srst"); |
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return retval; |
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} |
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else |
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@@ -745,7 +744,6 @@ int cortex_m3_assert_reset(target_t *target) |
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{ |
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if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) |
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{ |
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WARNING("srst resets test logic, too"); |
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retval = jtag_add_reset(1, 1); |
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} |
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} |
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@@ -756,13 +754,11 @@ int cortex_m3_assert_reset(target_t *target) |
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{ |
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if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) |
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{ |
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WARNING("srst resets test logic, too"); |
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retval = jtag_add_reset(1, 1); |
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} |
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if (retval == ERROR_JTAG_RESET_CANT_SRST) |
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{ |
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WARNING("can't assert srsrt"); |
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return retval; |
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} |
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else if (retval != ERROR_OK) |
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@@ -1136,16 +1132,16 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ |
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ERROR("JTAG failure %i",retval); |
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return ERROR_JTAG_DEVICE_ERROR; |
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} |
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/* DEBUG("load from core reg %i value 0x%x",num,*value); */ |
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DEBUG("load from core reg %i value 0x%x",num,*value); |
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} |
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else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ |
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{ |
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/* read other registers */ |
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/* cortex_m3_MRS(struct target_s *target, int num, u32* value) */ |
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u32 savedram; |
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u32 SYSm; |
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u32 instr; |
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SYSm = num & 0x1F; |
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ahbap_read_system_u32(swjdp, 0x20000000, &savedram); |
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instr = ARMV7M_T_MRS(0, SYSm); |
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ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MRS(0, SYSm)); |
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@@ -1158,7 +1154,10 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ |
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swjdp_transaction_endcheck(swjdp); |
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DEBUG("load from special reg %i value 0x%x", SYSm, *value); |
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} |
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else return ERROR_INVALID_ARGUMENTS; |
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else |
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{ |
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return ERROR_INVALID_ARGUMENTS; |
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} |
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return ERROR_OK; |
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} |
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@@ -1190,6 +1189,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty |
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u32 SYSm; |
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u32 instr; |
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SYSm = num & 0x1F; |
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ahbap_read_system_u32(swjdp, 0x20000000, &savedram); |
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instr = ARMV7M_T_MSR(SYSm, 0); |
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ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MSR(SYSm, 0)); |
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@@ -1203,7 +1203,10 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty |
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swjdp_transaction_endcheck(swjdp); |
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DEBUG("write special reg %i value 0x%x ", SYSm, value); |
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} |
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else return ERROR_INVALID_ARGUMENTS; |
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else |
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{ |
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return ERROR_INVALID_ARGUMENTS; |
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} |
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return ERROR_OK; |
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} |
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