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@@ -3184,24 +3184,29 @@ halt |
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@* |
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@* |
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In digital circuit design it is often refered to as ``clock |
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In digital circuit design it is often refered to as ``clock |
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syncronization'' the JTAG interface uses one clock (TCK or TCLK) |
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synchronisation'' the JTAG interface uses one clock (TCK or TCLK) |
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operating at some speed, your target is operating at another. The two |
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operating at some speed, your target is operating at another. The two |
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clocks are not syncronized, they are ``asynchronous'' |
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clocks are not synchronised, they are ``asynchronous'' |
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In order for the two to work together they must syncronize. Otherwise |
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In order for the two to work together they must be synchronised. Otherwise |
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the two systems will get out of sync with each other and nothing will |
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the two systems will get out of sync with each other and nothing will |
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work. There are 2 basic options. @b{1.} use a special circuit or |
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@b{2.} one clock must be some multile slower the the other. |
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work. There are 2 basic options. |
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@enumerate |
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@item |
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Use a special circuit. |
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@item |
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One clock must be some multiple slower the the other. |
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@end enumerate |
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@b{Does this really matter?} For some chips and some situations, this |
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@b{Does this really matter?} For some chips and some situations, this |
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is a non-issue (ie: A 500mhz ARM926) but for others - for example some |
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ATMEL SAM7 and SAM9 chips start operation from reset at 32khz - |
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is a non-issue (ie: A 500MHz ARM926) but for others - for example some |
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ATMEL SAM7 and SAM9 chips start operation from reset at 32kHz - |
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program/enable the oscillators and eventually the main clock. It is in |
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program/enable the oscillators and eventually the main clock. It is in |
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those critical times you must slow the jtag clock to sometimes 1 to |
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those critical times you must slow the jtag clock to sometimes 1 to |
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4khz. |
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4kHz. |
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Imagine debugging that 500mhz arm926 hand held battery powered device |
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that ``deep sleeps'' at 32khz between every keystroke. It can be |
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Imagine debugging that 500MHz ARM926 hand held battery powered device |
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that ``deep sleeps'' at 32kHz between every keystroke. It can be |
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painful. |
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painful. |
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@b{Solution #1 - A special circuit} |
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@b{Solution #1 - A special circuit} |
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@@ -3213,14 +3218,14 @@ The RTCK signal often found in some ARM chips is used to help with |
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this problem. ARM has a good description of the problem described at |
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this problem. ARM has a good description of the problem described at |
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this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked |
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this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked |
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28/nov/2008]. Link title: ``How does the jtag synchronisation logic |
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28/nov/2008]. Link title: ``How does the jtag synchronisation logic |
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work? / how does adaptive clocking working?''. |
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work? / how does adaptive clocking work?''. |
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The nice thing about adaptive clocking is that ``battery powered hand |
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The nice thing about adaptive clocking is that ``battery powered hand |
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held device example'' - the adaptiveness works perfectly all the |
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held device example'' - the adaptiveness works perfectly all the |
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time. One can set a break point or halt the system in the deep power |
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time. One can set a break point or halt the system in the deep power |
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down code, slow step out until the system speeds up. |
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down code, slow step out until the system speeds up. |
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@b{Solution #2 - Always works - but is slower} |
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@b{Solution #2 - Always works - but may be slower} |
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Often this is a perfectly acceptable solution. |
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Often this is a perfectly acceptable solution. |
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@@ -3230,7 +3235,7 @@ depending upon the chips on your board. @b{ARM Rule of thumb} Most ARM |
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based systems require an 8:1 division. @b{Xilinx Rule of thumb} is |
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based systems require an 8:1 division. @b{Xilinx Rule of thumb} is |
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1/12 the clock speed. |
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1/12 the clock speed. |
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Note: Many FTDI2232C based JTAG dongles are limited to 6mhz. |
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Note: Many FTDI2232C based JTAG dongles are limited to 6MHz. |
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You can still debug the 'lower power' situations - you just need to |
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You can still debug the 'lower power' situations - you just need to |
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manually adjust the clock speed at every step. While painful and |
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manually adjust the clock speed at every step. While painful and |
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@@ -3244,7 +3249,7 @@ this way. |
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To set the JTAG frequency use the command: |
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To set the JTAG frequency use the command: |
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@example |
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@example |
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# Example: 1.234mhz |
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# Example: 1.234MHz |
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jtag_khz 1234 |
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jtag_khz 1234 |
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@end example |
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@end example |
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@@ -3390,7 +3395,7 @@ You can use the ``scan_chain'' command to verify and display the tap order. |
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Many newer devices have multiple JTAG taps. For example: ST |
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Many newer devices have multiple JTAG taps. For example: ST |
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Microsystems STM32 chips have two taps, a ``boundary scan tap'' and |
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Microsystems STM32 chips have two taps, a ``boundary scan tap'' and |
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``cortexM3'' tap. Example: The STM32 reference manual, Document ID: |
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``CortexM3'' tap. Example: The STM32 reference manual, Document ID: |
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RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is |
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RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is |
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connected to the Boundary Scan Tap, which then connects to the |
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connected to the Boundary Scan Tap, which then connects to the |
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CortexM3 Tap, which then connects to the TDO pin. |
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CortexM3 Tap, which then connects to the TDO pin. |
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