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165 lines
3.6 KiB

  1. # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
  2. #
  3. # use combined on interfaces or targets that can't set TRST/SRST separately
  4. reset_config trst_and_srst srst_pulls_trst
  5. if { [info exists CHIPNAME] } {
  6. set _CHIPNAME $CHIPNAME
  7. } else {
  8. set _CHIPNAME cap7
  9. }
  10. if { [info exists ENDIAN] } {
  11. set _ENDIAN $ENDIAN
  12. } else {
  13. set _ENDIAN little
  14. }
  15. if { [info exists CPUTAPID] } {
  16. set _CPUTAPID $CPUTAPID
  17. } else {
  18. set _CPUTAPID 0x40700f0f
  19. }
  20. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  21. set _TARGETNAME $_CHIPNAME.cpu
  22. target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
  23. $_TARGETNAME configure -event reset-start {
  24. # start off real slow when we're running off internal RC oscillator
  25. adapter speed 32
  26. }
  27. proc peek32 {address} {
  28. mem2array t 32 $address 1
  29. return $t(0)
  30. }
  31. # Wait for an expression to be true with a timeout
  32. proc wait_state {expression} {
  33. for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
  34. if {[uplevel 1 $expression] == 0} {
  35. return
  36. }
  37. }
  38. return -code 1 "Timed out"
  39. }
  40. # Use a global variable here to be able to tinker interactively with
  41. # post reset jtag frequency.
  42. global post_reset_khz
  43. # Danger!!!! Even 16MHz kinda works with this target, but
  44. # it needs to be as low as 2000kHz to be stable.
  45. set post_reset_khz 2000
  46. $_TARGETNAME configure -event reset-init {
  47. echo "Configuring master clock"
  48. # disable watchdog
  49. mww 0xfffffd44 0xff008000
  50. # enable user reset
  51. mww 0xfffffd08 0xa5000001
  52. # Enable main oscillator
  53. mww 0xFFFFFc20 0x00000f01
  54. wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
  55. # Set PLLA to 96MHz
  56. mww 0xFFFFFc28 0x20072801
  57. wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
  58. # Select prescaler
  59. mww 0xFFFFFC30 0x00000004
  60. wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  61. # Select master clock to 48MHz
  62. mww 0xFFFFFC30 0x00000006
  63. wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  64. echo "Master clock ok."
  65. # Now that we're up and running, crank up speed!
  66. global post_reset_khz ; adapter speed $post_reset_khz
  67. echo "Configuring the SDRAM controller..."
  68. # Configure EBI Chip select for SDRAM
  69. mww 0xFFFFEF30 0x00000102
  70. # Enable clock on EBI PIOs
  71. mww 0xFFFFFC10 0x00000004
  72. # Configure PIO for SDRAM
  73. mww 0xFFFFF470 0xFFFF0000
  74. mww 0xFFFFF474 0x00000000
  75. mww 0xFFFFF404 0xFFFF0000
  76. # Configure SDRAMC CR
  77. mww 0xFFFFEA08 0xA63392F9
  78. # NOP command
  79. mww 0xFFFFEA00 0x1
  80. mww 0x20000000 0
  81. # Precharge All Banks command
  82. mww 0xFFFFEA00 0x2
  83. mww 0x20000000 0
  84. # Set 1st CBR
  85. mww 0xFFFFEA00 0x00000004
  86. mww 0x20000010 0x00000001
  87. # Set 2nd CBR
  88. mww 0xFFFFEA00 0x00000004
  89. mww 0x20000020 0x00000002
  90. # Set 3rd CBR
  91. mww 0xFFFFEA00 0x00000004
  92. mww 0x20000030 0x00000003
  93. # Set 4th CBR
  94. mww 0xFFFFEA00 0x00000004
  95. mww 0x20000040 0x00000004
  96. # Set 5th CBR
  97. mww 0xFFFFEA00 0x00000004
  98. mww 0x20000050 0x00000005
  99. # Set 6th CBR
  100. mww 0xFFFFEA00 0x00000004
  101. mww 0x20000060 0x00000006
  102. # Set 7th CBR
  103. mww 0xFFFFEA00 0x00000004
  104. mww 0x20000070 0x00000007
  105. # Set 8th CBR
  106. mww 0xFFFFEA00 0x00000004
  107. mww 0x20000080 0x00000008
  108. # Set LMR operation
  109. mww 0xFFFFEA00 0x00000003
  110. # Perform LMR burst=1, lat=2
  111. mww 0x20000020 0xCAFEDEDE
  112. # Set Refresh Timer
  113. mww 0xFFFFEA04 0x00000203
  114. # Set Normal mode
  115. mww 0xFFFFEA00 0x00000000
  116. mww 0x20000000 0x00000000
  117. #remap internal memory at address 0x0
  118. mww 0xffffef00 0x3
  119. echo "SDRAM configuration ok."
  120. }
  121. $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
  122. arm7_9 dcc_downloads enable
  123. arm7_9 fast_memory_access enable
  124. #set _FLASHNAME $_CHIPNAME.flash
  125. #flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432