You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

449 lines
16 KiB

  1. #################################################################################################
  2. # Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
  3. # based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
  4. # Kiwigrid GmbH ;#
  5. # Generated for In-Circuit i.MX53 SO-Dimm ;#
  6. #################################################################################################
  7. # The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
  8. source [find target/imx53.cfg]
  9. # Helper for common memory read/modify/write procedures
  10. source [find mem_helper.tcl]
  11. echo "i.MX53 SO-Dimm board lodaded."
  12. # Set reset type
  13. #reset_config srst_only
  14. adapter speed 3000
  15. # Slow speed to be sure it will work
  16. jtag_rclk 1000
  17. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
  18. $_TARGETNAME configure -event "reset-assert" {
  19. echo "Resetting ...."
  20. #cortex_a dbginit
  21. }
  22. $_TARGETNAME configure -event reset-init { sodimm_init }
  23. global AIPS1_BASE_ADDR
  24. set AIPS1_BASE_ADDR 0x53F00000
  25. global AIPS2_BASE_ADDR
  26. set AIPS2_BASE_ADDR 0x63F00000
  27. proc sodimm_init { } {
  28. echo "Reset-init..."
  29. ; # halt the CPU
  30. halt
  31. echo "HW version [format %x [mrw 0x48]]"
  32. dap apsel 1
  33. DCD
  34. ; # ARM errata ID #468414
  35. set tR [arm mrc 15 0 1 0 1]
  36. arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
  37. init_l2cc
  38. init_aips
  39. init_clock
  40. dap apsel 0
  41. ; # Force ARM state
  42. ; #reg cpsr 0x000001D3
  43. arm core_state arm
  44. jtag_rclk 3000
  45. # adapter speed 3000
  46. }
  47. # L2CC Cache setup/invalidation/disable
  48. proc init_l2cc { } {
  49. ; #/* explicitly disable L2 cache */
  50. ; #mrc 15, 0, r0, c1, c0, 1
  51. set tR [arm mrc 15 0 1 0 1]
  52. ; #bic r0, r0, #0x2
  53. ; #mcr 15, 0, r0, c1, c0, 1
  54. arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
  55. ; #/* reconfigure L2 cache aux control reg */
  56. ; #mov r0, #0xC0 /* tag RAM */
  57. ; #add r0, r0, #0x4 /* data RAM */
  58. ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
  59. ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
  60. ; #orr r0, r0, #(1 << 22) /* disable write allocate */
  61. ; #mcr 15, 1, r0, c9, c0, 2
  62. arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
  63. }
  64. # AIPS setup - Only setup MPROTx registers.
  65. # The PACR default values are good.
  66. proc init_aips { } {
  67. ; # Set all MPROTx to be non-bufferable, trusted for R/W,
  68. ; # not forced to user-mode.
  69. global AIPS1_BASE_ADDR
  70. global AIPS2_BASE_ADDR
  71. set VAL 0x77777777
  72. # dap apsel 1
  73. mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
  74. mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
  75. mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
  76. mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
  77. # dap apsel 0
  78. }
  79. proc init_clock { } {
  80. global AIPS1_BASE_ADDR
  81. global AIPS2_BASE_ADDR
  82. set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
  83. set CLKCTL_CCSR 0x0C
  84. set CLKCTL_CBCDR 0x14
  85. set CLKCTL_CBCMR 0x18
  86. set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
  87. set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
  88. set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
  89. set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
  90. set CLKCTL_CSCMR1 0x1C
  91. set CLKCTL_CDHIPR 0x48
  92. set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
  93. set CLKCTL_CSCDR1 0x24
  94. set CLKCTL_CCDR 0x04
  95. ; # Switch ARM to step clock
  96. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
  97. return
  98. echo "not returned"
  99. setup_pll $PLL1_BASE_ADDR 800
  100. setup_pll $PLL3_BASE_ADDR 400
  101. ; # Switch peripheral to PLL3
  102. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
  103. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
  104. while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
  105. setup_pll $PLL2_BASE_ADDR 400
  106. ; # Switch peripheral to PLL2
  107. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
  108. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
  109. ; # change uart clk parent to pll2
  110. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
  111. ; # make sure change is effective
  112. while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
  113. setup_pll $PLL3_BASE_ADDR 216
  114. setup_pll $PLL4_BASE_ADDR 455
  115. ; # Set the platform clock dividers
  116. mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
  117. mww [expr {$CCM_BASE_ADDR + 0x10}] 0
  118. ; # Switch ARM back to PLL 1.
  119. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
  120. ; # make uart div=6
  121. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
  122. ; # Restore the default values in the Gate registers
  123. mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
  124. mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
  125. mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
  126. mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
  127. mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
  128. mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
  129. mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
  130. mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
  131. mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
  132. ; # for cko - for ARM div by 8
  133. mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
  134. }
  135. proc setup_pll { PLL_ADDR CLK } {
  136. set PLL_DP_CTL 0x00
  137. set PLL_DP_CONFIG 0x04
  138. set PLL_DP_OP 0x08
  139. set PLL_DP_HFS_OP 0x1C
  140. set PLL_DP_MFD 0x0C
  141. set PLL_DP_HFS_MFD 0x20
  142. set PLL_DP_MFN 0x10
  143. set PLL_DP_HFS_MFN 0x24
  144. if {$CLK == 1000} {
  145. set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
  146. set DP_MFD [expr {12 - 1}]
  147. set DP_MFN 5
  148. } elseif {$CLK == 850} {
  149. set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
  150. set DP_MFD [expr {48 - 1}]
  151. set DP_MFN 41
  152. } elseif {$CLK == 800} {
  153. set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
  154. set DP_MFD [expr {3 - 1}]
  155. set DP_MFN 1
  156. } elseif {$CLK == 700} {
  157. set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
  158. set DP_MFD [expr {24 - 1}]
  159. set DP_MFN 7
  160. } elseif {$CLK == 600} {
  161. set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
  162. set DP_MFD [expr {4 - 1}]
  163. set DP_MFN 1
  164. } elseif {$CLK == 665} {
  165. set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
  166. set DP_MFD [expr {96 - 1}]
  167. set DP_MFN 89
  168. } elseif {$CLK == 532} {
  169. set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
  170. set DP_MFD [expr {24 - 1}]
  171. set DP_MFN 13
  172. } elseif {$CLK == 455} {
  173. set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
  174. set DP_MFD [expr {48 - 1}]
  175. set DP_MFN 71
  176. } elseif {$CLK == 400} {
  177. set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
  178. set DP_MFD [expr {3 - 1}]
  179. set DP_MFN 1
  180. } elseif {$CLK == 216} {
  181. set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
  182. set DP_MFD [expr {4 - 1}]
  183. set DP_MFN 3
  184. } else {
  185. error "Error (setup_dll): clock not found!"
  186. }
  187. mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
  188. mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
  189. mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
  190. mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
  191. mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
  192. mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
  193. mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
  194. mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
  195. mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
  196. while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
  197. }
  198. proc CPU_2_BE_32 { L } {
  199. return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
  200. }
  201. # Device Configuration Data
  202. proc DCD { } {
  203. # dap apsel 1
  204. #*========================================================================================== ======
  205. # Initialization script for 32 bit DDR3 (CS0+CS1)
  206. #*========================================================================================== ======
  207. # Remux D24/D25 to perform Flash-access
  208. mww 0x53fa818C 0x00000000 ; #EIM_RW
  209. mww 0x53fa8180 0x00000000 ; #EIM_CS0
  210. mww 0x53fa8188 0x00000000 ; #EIM_OE
  211. mww 0x53fa817C 0x00000000 ; #A16
  212. mww 0x53fa8178 0x00000000 ; #A17
  213. mww 0x53fa8174 0x00000000 ; #A18
  214. mww 0x53fa8170 0x00000000 ; #A19
  215. mww 0x53fa816C 0x00000000 ; #A20
  216. mww 0x53fa8168 0x00000000 ; #A21
  217. mww 0x53fa819C 0x00000000 ; #DA0
  218. mww 0x53fa81A0 0x00000000 ; #DA1
  219. mww 0x53fa81A4 0x00000000 ; #DA2
  220. mww 0x53fa81A8 0x00000000 ; #DA3
  221. mww 0x53fa81AC 0x00000000 ; #DA4
  222. mww 0x53fa81B0 0x00000000 ; #DA5
  223. mww 0x53fa81B4 0x00000000 ; #DA6
  224. mww 0x53fa81B8 0x00000000 ; #DA7
  225. mww 0x53fa81BC 0x00000000 ; #DA8
  226. mww 0x53fa81C0 0x00000000 ; #DA9
  227. mww 0x53fa81C4 0x00000000 ; #DA10
  228. mww 0x53fa81C8 0x00000000 ; #DA11
  229. mww 0x53fa81CC 0x00000000 ; #DA12
  230. mww 0x53fa81D0 0x00000000 ; #DA13
  231. mww 0x53fa81D4 0x00000000 ; #DA14
  232. mww 0x53fa81D8 0x00000000 ; #DA15
  233. mww 0x53fa8118 0x00000000 ; #D16
  234. mww 0x53fa811C 0x00000000 ; #D17
  235. mww 0x53fa8120 0x00000000 ; #D18
  236. mww 0x53fa8124 0x00000000 ; #D19
  237. mww 0x53fa8128 0x00000000 ; #D20
  238. mww 0x53fa812C 0x00000000 ; #D21
  239. mww 0x53fa8130 0x00000000 ; #D22
  240. mww 0x53fa8134 0x00000000 ; #D23
  241. mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
  242. mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
  243. mww 0x53fa8144 0x00000000 ; #D26
  244. mww 0x53fa8148 0x00000000 ; #D27
  245. mww 0x53fa814C 0x00000000 ; #D28
  246. mww 0x53fa8150 0x00000000 ; #D29
  247. mww 0x53fa8154 0x00000000 ; #D30
  248. mww 0x53fa8158 0x00000000 ; #D31
  249. # DDR3 IOMUX configuration
  250. #* Global pad control options */
  251. mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
  252. mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
  253. mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
  254. mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
  255. mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
  256. mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
  257. mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
  258. mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
  259. mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
  260. mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
  261. mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
  262. mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
  263. mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
  264. mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
  265. mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
  266. mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
  267. mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
  268. # mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
  269. mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
  270. mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
  271. mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
  272. mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
  273. mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
  274. mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
  275. mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
  276. # mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
  277. # mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
  278. # mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
  279. # mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
  280. #* Data bus byte lane pad drive strength control options */
  281. # mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
  282. # mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
  283. # mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
  284. # mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
  285. # mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
  286. # mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
  287. # mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
  288. # mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
  289. # mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
  290. # mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
  291. # mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
  292. # mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
  293. #* SDCLK pad drive strength control options */
  294. # mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
  295. # mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
  296. #* Control and addr bus pad drive strength control options */
  297. # mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
  298. # mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
  299. # mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
  300. # mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
  301. # mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
  302. # mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
  303. # Initialize DDR3 memory - Micron MT41J128M16-187Er
  304. #** Keep for now, same setting as CPU3 board **#
  305. mww 0x63fd901c 0x00008000
  306. # mww 0x63fd904c 0x01680172 ; #write leveling reg 0
  307. # mww 0x63fd9050 0x0021017f ; #write leveling reg 1
  308. mww 0x63fd9088 0x32383535 ; #read delay lines
  309. mww 0x63fd9090 0x40383538 ; #write delay lines
  310. # mww 0x63fd90F8 0x00000800 ; #Measure unit
  311. mww 0x63fd907c 0x0136014d ; #DQS gating 0
  312. mww 0x63fd9080 0x01510141 ; #DQS gating 1
  313. #* CPU3 Board settingr
  314. # Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
  315. # mww 0x63fd9018 0x00091740 ; #Misc register:
  316. #* Quick Silver board setting
  317. # Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
  318. mww 0x63fd9018 0x00011740 ; #Misc register
  319. # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
  320. # mww 0x63fd9000 0xc3190000 ; #Main control register
  321. # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
  322. mww 0x63fd9000 0x83190000 ; #Main control register
  323. # tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
  324. mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
  325. # tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
  326. mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
  327. # tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
  328. mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
  329. mww 0x63fd902c 0x000026d2 ; #command delay (default)
  330. mww 0x63fd9030 0x009f0e21 ; #out of reset delays
  331. # Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
  332. mww 0x63fd9008 0x12273030 ; #ODT timings
  333. # tCKE=3; tCKSRX=5; tCKSRE=5
  334. mww 0x63fd9004 0x0002002d
  335. #Power down control
  336. #**********************************
  337. #DDR device configuration:
  338. #**********************************
  339. #**********************************
  340. # CS0:
  341. #**********************************
  342. mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
  343. # Full array self refresh
  344. # Rtt_WR disabled (no ODT at IO CMOS operation)
  345. # Manual self refresh
  346. # CWS=5
  347. mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
  348. mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
  349. # out impedance = RZQ/7
  350. # Rtt_nom disabled (no ODT at IO CMOS operation)
  351. # Aditive latency off
  352. # write leveling disabled
  353. # tdqs (differential?) disabled
  354. mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
  355. mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
  356. #**********************************
  357. # CS1:
  358. #**********************************
  359. # mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
  360. # mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
  361. # mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
  362. # mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
  363. # mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
  364. #**********************************
  365. mww 0x63fd9020 0x00001800 ; # Refresh control register
  366. mww 0x63fd9040 0x04b80003 ; # ZQ HW control
  367. mww 0x63fd9058 0x00022227 ; # ODT control register
  368. mww 0x63fd901c 0x00000000
  369. # CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
  370. # mww 0x53FA8314 = 0
  371. # mww 0x53FA8320 0x4
  372. # mww 0x53FD4060 0x01e900f0
  373. # dap apsel 0
  374. }
  375. # IRAM
  376. $_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
  377. flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME
  378. # vim:filetype=tcl