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46 lines
1.3 KiB

  1. # This is a stm32h750b-dk with a single STM32H750XBH6 chip.
  2. # www.st.com/en/product/stm32h750b-dk.html
  3. #
  4. # This is for using the onboard STLINK
  5. source [find interface/stlink.cfg]
  6. transport select hla_swd
  7. set CHIPNAME stm32h750xbh6
  8. # enable stmqspi
  9. if {![info exists QUADSPI]} {
  10. set QUADSPI 1
  11. }
  12. source [find target/stm32h7x.cfg]
  13. source [find board/stm32h7x_dual_qspi.cfg]
  14. $_CHIPNAME.cpu0 configure -event reset-init {
  15. global QUADSPI
  16. mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
  17. mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on
  18. mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
  19. mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
  20. mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
  21. mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2
  22. mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
  23. mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
  24. mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
  25. mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1
  26. sleep 1
  27. mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock
  28. sleep 1
  29. adapter speed 24000
  30. if { $QUADSPI } {
  31. qspi_init 1
  32. }
  33. }