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  1. #
  2. # Altera cyclone V SoC family, 5Cxxx
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME fpgasoc
  8. }
  9. # CoreSight Debug Access Port
  10. if { [info exists DAP_TAPID] } {
  11. set _DAP_TAPID $DAP_TAPID
  12. } else {
  13. set _DAP_TAPID 0x4ba00477
  14. }
  15. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
  16. -expected-id $_DAP_TAPID
  17. # Subsidiary TAP: fpga
  18. if { [info exists FPGA_TAPID] } {
  19. set _FPGA_TAPID $FPGA_TAPID
  20. } else {
  21. set _FPGA_TAPID 0x02d020dd
  22. }
  23. jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
  24. #
  25. # Cortex-A9 target
  26. #
  27. # GDB target: Cortex-A9, using DAP, configuring only one core
  28. # Base addresses of cores:
  29. # core 0 - 0x80110000
  30. # core 1 - 0x80112000
  31. # Slow speed to be sure it will work
  32. adapter speed 1000
  33. set _TARGETNAME1 $_CHIPNAME.cpu.0
  34. set _TARGETNAME2 $_CHIPNAME.cpu.1
  35. # A9 core 0
  36. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  37. target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
  38. -coreid 0 -dbgbase 0x80110000
  39. $_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
  40. $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
  41. # A9 core 1
  42. #target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
  43. # -coreid 1 -dbgbase 0x80112000
  44. #$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
  45. #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
  46. proc cycv_dbginit {target} {
  47. # General Cortex-A8/A9 debug initialisation
  48. cortex_a dbginit
  49. }