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  1. #
  2. # Freescale i.MX6 series
  3. #
  4. # Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
  5. #
  6. # Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
  7. #
  8. if { [info exists CHIPNAME] } {
  9. set _CHIPNAME $CHIPNAME
  10. } else {
  11. set _CHIPNAME imx6
  12. }
  13. # CoreSight Debug Access Port
  14. if { [info exists DAP_TAPID] } {
  15. set _DAP_TAPID $DAP_TAPID
  16. } else {
  17. set _DAP_TAPID 0x4ba00477
  18. }
  19. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
  20. -expected-id $_DAP_TAPID
  21. # SDMA / no IDCODE
  22. jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
  23. # System JTAG Controller
  24. # List supported SJC TAPIDs from imx reference manuals:
  25. set _SJC_TAPID_6Q 0x0191c01d
  26. set _SJC_TAPID_6D 0x0191e01d
  27. set _SJC_TAPID_6QP 0x3191c01d
  28. set _SJC_TAPID_6DP 0x3191d01d
  29. set _SJC_TAPID_6DL 0x0891a01d
  30. set _SJC_TAPID_6S 0x0891b01d
  31. set _SJC_TAPID_6SL 0x0891f01d
  32. set _SJC_TAPID_6SLL 0x088c201d
  33. # Allow external override of the first SJC TAPID
  34. if { [info exists SJC_TAPID] } {
  35. set _SJC_TAPID $SJC_TAPID
  36. } else {
  37. set _SJC_TAPID $_SJC_TAPID_6Q
  38. }
  39. jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
  40. -ignore-version \
  41. -expected-id $_SJC_TAPID \
  42. -expected-id $_SJC_TAPID_6QP \
  43. -expected-id $_SJC_TAPID_6DP \
  44. -expected-id $_SJC_TAPID_6D \
  45. -expected-id $_SJC_TAPID_6DL \
  46. -expected-id $_SJC_TAPID_6S \
  47. -expected-id $_SJC_TAPID_6SL \
  48. -expected-id $_SJC_TAPID_6SLL
  49. # GDB target: Cortex-A9, using DAP, configuring only one core
  50. # Base addresses of cores:
  51. # core 0 - 0x82150000
  52. # core 1 - 0x82152000
  53. # core 2 - 0x82154000
  54. # core 3 - 0x82156000
  55. set _TARGETNAME $_CHIPNAME.cpu.0
  56. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  57. target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
  58. -coreid 0 -dbgbase 0x82150000
  59. # some TCK cycles are required to activate the DEBUG power domain
  60. jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
  61. proc imx6_dbginit {target} {
  62. # General Cortex-A8/A9 debug initialisation
  63. cortex_a dbginit
  64. }
  65. # Slow speed to be sure it will work
  66. adapter speed 1000
  67. $_TARGETNAME configure -event reset-start { adapter speed 1000 }
  68. $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"