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  1. #
  2. # configuration file for NXP i.MX8M family of SoCs
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME imx8m
  8. }
  9. if { [info exists CHIPCORES] } {
  10. set _cores $CHIPCORES
  11. } else {
  12. set _cores 1
  13. }
  14. # CoreSight Debug Access Port
  15. if { [info exists DAP_TAPID] } {
  16. set _DAP_TAPID $DAP_TAPID
  17. } else {
  18. set _DAP_TAPID 0x5ba00477
  19. }
  20. # the DAP tap
  21. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
  22. -expected-id $_DAP_TAPID
  23. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  24. set _TARGETNAME $_CHIPNAME.a53
  25. set _CTINAME $_CHIPNAME.cti
  26. set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
  27. set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
  28. for { set _core 0 } { $_core < $_cores } { incr _core } {
  29. cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
  30. -baseaddr [lindex $CTIBASE $_core]
  31. set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
  32. -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
  33. if { $_core != 0 } {
  34. # non-boot core examination may fail
  35. set _command "$_command -defer-examine"
  36. set _smp_command "$_smp_command $_TARGETNAME.$_core"
  37. } else {
  38. set _smp_command "target smp $_TARGETNAME.$_core"
  39. }
  40. eval $_command
  41. }
  42. eval $_smp_command
  43. # declare the auxiliary Cortex-M4 core on AP #4
  44. target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
  45. -defer-examine
  46. # AHB-AP for direct access to soc bus
  47. target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
  48. # default target is A53 core 0
  49. targets $_TARGETNAME.0