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73 lines
1.6 KiB

  1. source [find target/swj-dp.tcl]
  2. adapter speed 500
  3. if { [info exists CHIPNAME] } {
  4. set _CHIPNAME $CHIPNAME
  5. } else {
  6. set _CHIPNAME lpc4350
  7. }
  8. #
  9. # M4 JTAG mode TAP
  10. #
  11. if { [info exists M4_JTAG_TAPID] } {
  12. set _M4_JTAG_TAPID $M4_JTAG_TAPID
  13. } else {
  14. set _M4_JTAG_TAPID 0x4ba00477
  15. }
  16. #
  17. # M4 SWD mode TAP
  18. #
  19. if { [info exists M4_SWD_TAPID] } {
  20. set _M4_SWD_TAPID $M4_SWD_TAPID
  21. } else {
  22. set _M4_SWD_TAPID 0x2ba01477
  23. }
  24. if { [using_jtag] } {
  25. set _M4_TAPID $_M4_JTAG_TAPID
  26. } {
  27. set _M4_TAPID $_M4_SWD_TAPID
  28. }
  29. #
  30. # M0 TAP
  31. #
  32. if { [info exists M0_JTAG_TAPID] } {
  33. set _M0_JTAG_TAPID $M0_JTAG_TAPID
  34. } else {
  35. set _M0_JTAG_TAPID 0x0ba01477
  36. }
  37. swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
  38. -expected-id $_M4_TAPID
  39. dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
  40. target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
  41. if { [using_jtag] } {
  42. swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
  43. -expected-id $_M0_JTAG_TAPID
  44. dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
  45. target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
  46. }
  47. # LPC4350 has 96+32 KB SRAM
  48. if { [info exists WORKAREASIZE] } {
  49. set _WORKAREASIZE $WORKAREASIZE
  50. } else {
  51. set _WORKAREASIZE 0x20000
  52. }
  53. $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
  54. -work-area-size $_WORKAREASIZE -work-area-backup 0
  55. if {![using_hla]} {
  56. # on this CPU we should use VECTRESET to perform a soft reset and
  57. # manually reset the periphery
  58. # SRST or SYSRESETREQ disable the debug interface for the time of
  59. # the reset and will not fit our requirements for a consistent debug
  60. # session
  61. cortex_m reset_config vectreset
  62. }