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  1. #
  2. # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
  3. #
  4. adapter speed 500
  5. if { [info exists CHIPNAME] } {
  6. set _CHIPNAME $CHIPNAME
  7. } else {
  8. set _CHIPNAME lpc4370
  9. }
  10. #
  11. # M4 JTAG mode TAP
  12. #
  13. if { [info exists M4_JTAG_TAPID] } {
  14. set _M4_JTAG_TAPID $M4_JTAG_TAPID
  15. } else {
  16. set _M4_JTAG_TAPID 0x4ba00477
  17. }
  18. #
  19. # M4 SWD mode TAP
  20. #
  21. if { [info exists M4_SWD_TAPID] } {
  22. set _M4_SWD_TAPID $M4_SWD_TAPID
  23. } else {
  24. set _M4_SWD_TAPID 0x2ba01477
  25. }
  26. source [find target/swj-dp.tcl]
  27. if { [using_jtag] } {
  28. set _M4_TAPID $_M4_JTAG_TAPID
  29. } else {
  30. set _M4_TAPID $_M4_SWD_TAPID
  31. }
  32. #
  33. # M0 TAP
  34. #
  35. if { [info exists M0_JTAG_TAPID] } {
  36. set _M0_JTAG_TAPID $M0_JTAG_TAPID
  37. } else {
  38. set _M0_JTAG_TAPID 0x0ba01477
  39. }
  40. swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
  41. -expected-id $_M4_TAPID
  42. dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
  43. target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
  44. # LPC4370 has 96+32 KB contiguous SRAM
  45. if { [info exists WORKAREASIZE] } {
  46. set _WORKAREASIZE $WORKAREASIZE
  47. } else {
  48. set _WORKAREASIZE 0x20000
  49. }
  50. $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
  51. -work-area-size $_WORKAREASIZE -work-area-backup 0
  52. if { [using_jtag] } {
  53. jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
  54. -expected-id $_M0_JTAG_TAPID
  55. jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
  56. -expected-id $_M0_JTAG_TAPID
  57. dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
  58. dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
  59. target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
  60. target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
  61. # 32+8+32 KB SRAM
  62. $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
  63. -work-area-size 0x92000 -work-area-backup 0
  64. # 16+2 KB M0 subsystem SRAM
  65. $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
  66. -work-area-size 0x4800 -work-area-backup 0
  67. # Default to the Cortex-M4
  68. targets $_CHIPNAME.m4
  69. }
  70. if { ![using_hla] } {
  71. cortex_m reset_config vectreset
  72. }