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  1. # NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
  2. # Copyright (C) 2018 by Jean-Christian de Rivaz
  3. # Based on NXP proposal https://community.nxp.com/message/1011149
  4. # Many thanks to Dries Moors from NXP support.
  5. # SWD only transport
  6. source [find target/swj-dp.tcl]
  7. source [find mem_helper.tcl]
  8. if { [info exists CHIPNAME] } {
  9. set _CHIPNAME $CHIPNAME
  10. } else {
  11. set _CHIPNAME lpc8nxx
  12. }
  13. swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0
  14. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  15. set _TARGETNAME $_CHIPNAME.cpu
  16. target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
  17. if {![using_hla]} {
  18. # If srst is not fitted use SYSRESETREQ to perform a soft reset
  19. cortex_m reset_config sysresetreq
  20. }
  21. adapter srst delay 100
  22. $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
  23. flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500
  24. echo "*********************************************************************************"
  25. echo "* !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!"
  26. echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also"
  27. echo "* unpowered. These modes can be entered by firmware. The default firmware image"
  28. echo "* (flashed in production) makes use of this. Best is to avoid these power modes"
  29. echo "* during development, and only later add them when the functionality is complete."
  30. echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is"
  31. echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST"
  32. echo "* signal to the chip RESETN pin and add the following in your configuration:"
  33. echo "* reset_config srst_only; flash init; catch init; reset"
  34. echo "* But if the actual firmware immediately set the power down mode after reset,"
  35. echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In"
  36. echo "* that case the only solution is to apply a NFC field to keep the SWD powered."
  37. echo "*********************************************************************************"
  38. # Using soft-reset 'reset_config none' is strongly discouraged.
  39. # RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.
  40. # Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.
  41. #
  42. proc set_sysclk_500khz {} {
  43. set SYSCLKCTRL 0x40048020
  44. set SYSCLKUEN 0x40048024
  45. mww $SYSCLKUEN 0
  46. mmw $SYSCLKCTRL 0x8 0xe
  47. mww $SYSCLKUEN 1
  48. echo "Notice: sysclock set to 500kHz."
  49. }
  50. # Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
  51. # Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
  52. # Bit Symbol Value Description
  53. # 0 map - interrupt vector remap. 0 after boot.
  54. # 0 interrupt vector reside in Flash
  55. # 1 interrupt vector reside in SRAM
  56. # 5:1 offset - system memory remap offset. 00000b after boot.
  57. # 00000b interrupt vectors in flash or remapped to SRAM but no offset
  58. # 00001b -
  59. # 00111b interrupt vectors offset in flash or SRAM to 1K word segment
  60. # 01000b -
  61. # 11111b interrupt vectors offset in flash to 1K word segment 8 to 31
  62. # 31:6 reserved
  63. #
  64. proc set_no_remap {} {
  65. mww 0x40048000 0x00
  66. echo "Notice: interrupt vector set to no remap."
  67. }
  68. $_TARGETNAME configure -event reset-init {
  69. set_sysclk_500khz
  70. set_no_remap
  71. }