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  1. # OMAP4460
  2. if { [info exists CHIPNAME] } {
  3. set _CHIPNAME $CHIPNAME
  4. } else {
  5. set _CHIPNAME omap4460
  6. }
  7. # Although the OMAP4430 supposedly has an ICEpick-D, only the
  8. # ICEpick-C router commands seem to work.
  9. # See http://processors.wiki.ti.com/index.php/ICEPICK
  10. source [find target/icepick.cfg]
  11. #
  12. # A9 DAP
  13. #
  14. if { [info exists DAP_TAPID] } {
  15. set _DAP_TAPID $DAP_TAPID
  16. } else {
  17. set _DAP_TAPID 0x3BA00477
  18. }
  19. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
  20. -expected-id $_DAP_TAPID -disable
  21. jtag configure $_CHIPNAME.cpu -event tap-enable \
  22. "icepick_c_tapenable $_CHIPNAME.jrc 9"
  23. #
  24. # M3 DAPs, one per core
  25. #
  26. if { [info exists M3_DAP_TAPID] } {
  27. set _M3_DAP_TAPID $M3_DAP_TAPID
  28. } else {
  29. set _M3_DAP_TAPID 0x4BA00477
  30. }
  31. jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
  32. -expected-id $_M3_DAP_TAPID -disable
  33. jtag configure $_CHIPNAME.m31 -event tap-enable \
  34. "icepick_c_tapenable $_CHIPNAME.jrc 5"
  35. jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
  36. -expected-id $_M3_DAP_TAPID -disable
  37. jtag configure $_CHIPNAME.m30 -event tap-enable \
  38. "icepick_c_tapenable $_CHIPNAME.jrc 4"
  39. #
  40. # ICEpick-D JRC (JTAG route controller)
  41. #
  42. if { [info exists JRC_TAPID] } {
  43. set _JRC_TAPID $JRC_TAPID
  44. } else {
  45. set _JRC_TAPID 0x2b94e02f
  46. set _JRC_TAPID2 0x1b85202f
  47. }
  48. # PandaBoard REV EA1 (PEAP platforms)
  49. if { [info exists JRC_TAPID2] } {
  50. set _JRC_TAPID2 $JRC_TAPID2
  51. } else {
  52. set _JRC_TAPID2 0x1b85202f
  53. }
  54. jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  55. -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
  56. # Required by ICEpick to power-up the debug domain
  57. jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
  58. #
  59. # GDB target: Cortex-A9, using DAP
  60. #
  61. # The debugger can connect to either core of the A9, but currently
  62. # not both simultaneously. Change -coreid to 1 to connect to the
  63. # second core.
  64. #
  65. set _TARGETNAME $_CHIPNAME.cpu
  66. # APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
  67. # 0x80000000 is cpu0 coresight region
  68. #
  69. #
  70. # CORTEX_A8_PADDRDBG_CPU_SHIFT 13
  71. # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
  72. set _coreid 0
  73. set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
  74. echo "Using dbgbase = [format 0x%x $_dbgbase]"
  75. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  76. target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
  77. -coreid 0 -dbgbase $_dbgbase
  78. # SRAM: 56KiB at 0x4030.0000
  79. $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
  80. #
  81. # M3 targets, separate TAP/DAP for each core
  82. #
  83. dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
  84. dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
  85. target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
  86. target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
  87. # Once the JRC is up, enable our TAPs
  88. jtag configure $_CHIPNAME.jrc -event setup "
  89. jtag tapenable $_CHIPNAME.cpu
  90. jtag tapenable $_CHIPNAME.m30
  91. jtag tapenable $_CHIPNAME.m31
  92. "
  93. # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
  94. # ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
  95. set PRM_RSTCTRL 0x4A307B00
  96. $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
  97. $_CHIPNAME.m30 configure -event reset-assert { }
  98. $_CHIPNAME.m31 configure -event reset-assert { }
  99. # Soft breakpoints don't currently work due to broken cache handling
  100. gdb_breakpoint_override hard