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  1. #
  2. # Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
  3. # PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
  4. # the same Flash/RAM/MMIO address space.
  5. #
  6. source [find target/swj-dp.tcl]
  7. adapter speed 1000
  8. global _CHIPNAME
  9. if { [info exists CHIPNAME] } {
  10. set _CHIPNAME $CHIPNAME
  11. } else {
  12. set _CHIPNAME psoc6
  13. }
  14. global TARGET
  15. set TARGET $_CHIPNAME.cpu
  16. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
  17. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  18. # Is CM0 Debugging enabled ?
  19. global _ENABLE_CM0
  20. if { [info exists ENABLE_CM0] } {
  21. set _ENABLE_CM0 $ENABLE_CM0
  22. } else {
  23. set _ENABLE_CM0 1
  24. }
  25. # Is CM4 Debugging enabled ?
  26. global _ENABLE_CM4
  27. if { [info exists ENABLE_CM4] } {
  28. set _ENABLE_CM4 $ENABLE_CM4
  29. } else {
  30. set _ENABLE_CM4 1
  31. }
  32. global _WORKAREASIZE_CM0
  33. if { [info exists WORKAREASIZE_CM0] } {
  34. set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
  35. } else {
  36. set _WORKAREASIZE_CM0 0x4000
  37. }
  38. global _WORKAREASIZE_CM4
  39. if { [info exists WORKAREASIZE_CM4] } {
  40. set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
  41. } else {
  42. set _WORKAREASIZE_CM4 0x4000
  43. }
  44. global _WORKAREAADDR_CM0
  45. if { [info exists WORKAREAADDR_CM0] } {
  46. set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
  47. } else {
  48. set _WORKAREAADDR_CM0 0x08000000
  49. }
  50. global _WORKAREAADDR_CM4
  51. if { [info exists WORKAREAADDR_CM4] } {
  52. set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
  53. } else {
  54. set _WORKAREAADDR_CM4 0x08000000
  55. }
  56. proc init_reset { mode } {
  57. global RESET_MODE
  58. set RESET_MODE $mode
  59. if {[using_jtag]} {
  60. jtag arp_init-reset
  61. }
  62. }
  63. # Utility to make 'reset halt' work as reset;halt on a target
  64. # It does not prevent running code after reset
  65. proc psoc6_deassert_post { target } {
  66. # PSoC6 cleared AP registers including TAR during reset
  67. # Force examine to synchronize OpenOCD target status
  68. $target arp_examine
  69. global RESET_MODE
  70. global TARGET
  71. if { $RESET_MODE ne "run" } {
  72. $target arp_poll
  73. $target arp_poll
  74. set st [$target curstate]
  75. if { $st eq "reset" } {
  76. # we assume running state follows
  77. # if reset accidentally halts, waiting is useless
  78. catch { $target arp_waitstate running 100 }
  79. set st [$target curstate]
  80. }
  81. if { $st eq "running" } {
  82. echo "$target: Ran after reset and before halt..."
  83. if { $target eq "${TARGET}.cm0" } {
  84. # Try to cleanly reset whole system
  85. # and halt the CM0 at entry point
  86. psoc6 reset_halt
  87. $target arp_waitstate halted 100
  88. } else {
  89. $target arp_halt
  90. }
  91. }
  92. }
  93. }
  94. if { $_ENABLE_CM0 } {
  95. target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
  96. ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
  97. flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0
  98. flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 ${TARGET}.cm0
  99. flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0
  100. flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
  101. flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
  102. flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
  103. ${TARGET}.cm0 cortex_m reset_config sysresetreq
  104. ${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
  105. }
  106. if { $_ENABLE_CM4 } {
  107. target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
  108. ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
  109. flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4
  110. flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 ${TARGET}.cm4
  111. flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4
  112. flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
  113. flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
  114. flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
  115. ${TARGET}.cm4 cortex_m reset_config vectreset
  116. ${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
  117. }
  118. if { $_ENABLE_CM0 } {
  119. # Use CM0+ by default on dual-core devices
  120. targets ${TARGET}.cm0
  121. }
  122. if {[using_jtag]} {
  123. jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
  124. }